The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
Mahesh Mehendale: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mahesh Mehendale, Amit Sinha, Sunil D. Sherlekar
    Low Power Realization of FIR Filters Implemented using Distributed Arithmetic. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:151-156 [Conf]
  2. Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
    Techniques for low power realization for FIR filters. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  3. Chi-Foon Chan, Deirdre Hanford, Jian Yue Pan, Narendra V. Shenoy, Mahesh Mehendale, A. Vasudevan, Shaojun Wei
    Emerging markets: design goes global. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:195- [Conf]
  4. Mahesh Mehendale
    MIM: Logic Module Independent Technology Mapping for Design and Evaluation of Antifuse-based FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:219-223 [Conf]
  5. Mahesh Mehendale, G. Venkatesh, Sunil D. Sherlekar
    Optimized Code Generation of Multiplication-free Linear Transforms. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:41-46 [Conf]
  6. Subash G. Chandar, Mahesh Mehendale, R. Govindarajan
    Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-Configurable Encoding. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:631-634 [Conf]
  7. Mahesh Mehendale, P. Murugavel, M. Poornima
    SLIM: A System for ASIC Library Management. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:144-147 [Conf]
  8. Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
    Synthesis of multiplier-less FIR filters with minimum number of additions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:668-671 [Conf]
  9. M. N. Mahesh, Mahesh Mehendale
    Improving performance of high precision signal processing algorithms on programmable DSPs. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 1999, pp:488-491 [Conf]
  10. Amitabh Menon, S. K. Nandy, Mahesh Mehendale
    Multivoltage scheduling with voltage-partitioned variable storage. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:298-301 [Conf]
  11. Vikas Agrawal, Anand Pande, Mahesh Mehendale
    High Level Synthesis Of Multi-Precision Data Flow Graphs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:411-416 [Conf]
  12. Ajit Gupte, Mahesh Mehendale, Ramesh Ramamritham, Deepa Nair
    Performance Considerations in Embedded DSP based System-On-a-Chip Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:36-41 [Conf]
  13. Mahesh Mehendale
    Challenges in the Design of Embedded Real-time DSP SoCs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:507-511 [Conf]
  14. Mahesh Mehendale
    SoC - The Road Ahead. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:40- [Conf]
  15. Mahesh Mehendale
    Impact of Logic Module Routing Flexibility on the Routability of Antifuse-Based Channelled FPGA Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:233-236 [Conf]
  16. Mahesh Mehendale, Santhosh Kumar Amanna
    Functional Verification of Programmable DSP Cores. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:16-17 [Conf]
  17. Mahesh Mehendale, Biswadip Mitra
    An Integrated Approach to State Assignment and Sequential Element Selection for FSM Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:369-372 [Conf]
  18. Mahesh Mehendale, M. K. Ram Prasad
    AATMA: an algorithm for technology mapping for antifuse-based FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:69-74 [Conf]
  19. Mahesh Mehendale, Kaushik Roy
    Estimating Area Efficiency of Antifuse Based Channelled FPGA Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:100-103 [Conf]
  20. Mahesh Mehendale, Somdipta Basu Roy, Sunil D. Sherlekar, G. Venkatesh
    Coefficient Transformations for Area-Efficient Implementation of Multiplier-less FIR Filters. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:110-115 [Conf]
  21. M. N. Mahesh, Mahesh Mehendale
    Low Power Realization of Residue Number System Based FIR Filters. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:30-33 [Conf]
  22. Mahesh Mehendale, Sunil D. Sherlekar
    Power Reduction Techniques for Portable DSP Applications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:3- [Conf]
  23. Mahesh Mehendale, Sunil D. Sherlekar
    Low Power Code Generation of Multiplication-free Linear Transforms. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:42-47 [Conf]
  24. Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
    Low power realization of FIR filters using multirate architectures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:370-375 [Conf]
  25. Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
    Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR Filters. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:124-129 [Conf]
  26. Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
    Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:12-17 [Conf]
  27. Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
    Extensions to Programmable DSP architectures for Reduced Power Dissipation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:37-0 [Conf]
  28. M. N. Mahesh, Satrajit Gupta, Mahesh Mehendale
    Improving Area Efficiency of Residue Number System based Implementation of DSP Algorithms. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:340-345 [Conf]
  29. Amit Sinha, Mahesh Mehendale
    mproving Area Efficiency of FIR Filters Implemented Using Distributed Arithmetic. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:104-109 [Conf]
  30. Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
    Low-power realization of FIR filters on programmable DSPs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:546-553 [Journal]
  31. Subash G. Chandar, Mahesh Mehendale, R. Govindarajan
    Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:44, n:3, pp:245-267 [Journal]

Search in 0.003secs, Finished in 0.004secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002