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Odysseas G. Koufopavlou:
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Publications of Author
- Odysseas G. Koufopavlou, Ahmed N. Tantawy, Martina Zitterbart
An ATM Communication Workstation. [Citation Graph (0, 0)][DBLP] Broadband Islands, 1993, pp:93-104 [Conf]
- Labros Bisdounis, Odysseas G. Koufopavlou, Constantinos E. Goutis, Spiridon Nikolaidis
Switching Response Modeling of the CMOS Inverter for Sub-micron Devices. [Citation Graph (0, 0)][DBLP] DATE, 1998, pp:729-0 [Conf]
- Odysseas G. Koufopavlou, Ahmed N. Tantawy, Martina Zitterbart
A Comparison of Gigabit Router Architectures. [Citation Graph (0, 0)][DBLP] HPN, 1994, pp:107-121 [Conf]
- Efstathios D. Kyriakis-Bitzaros, Odysseas G. Koufopavlou, Constantinos E. Goutis
Space-Time Representation of Iterative Algorithms and The Design of Regular Processor Arrays. [Citation Graph (0, 0)][DBLP] ICPP, 1993, pp:2-9 [Conf]
- Abdoul Rjoub, Odysseas G. Koufopavlou
Multithreshold Voltage Technology for Low Power Bus Architecture. [Citation Graph (0, 0)][DBLP] VLSI, 1999, pp:219-232 [Conf]
- Apostolos P. Fournaris, Odysseas G. Koufopavlou
A new RSA encryption architecture and hardware implementation based on optimized Montgomery multiplication. [Citation Graph (0, 0)][DBLP] ISCAS (5), 2005, pp:4645-4648 [Conf]
- Paris Kitsos, Michalis D. Galanis, Odysseas G. Koufopavlou
A RAM-based FPGA implementation of the 64-bit MISTY1 block cipher. [Citation Graph (0, 0)][DBLP] ISCAS (5), 2005, pp:4641-4644 [Conf]
- Nicolas Sklavos, Odysseas G. Koufopavlou
On the hardware implementations of the SHA-2 (256, 384, 512) hash functions. [Citation Graph (0, 0)][DBLP] ISCAS (5), 2003, pp:153-156 [Conf]
- Abdoul Rjoub, M. Alrousan, O. Jarrah, Odysseas G. Koufopavlou
Multi-level low swing voltage values for low power design applications. [Citation Graph (0, 0)][DBLP] ISCAS (4), 2001, pp:590-593 [Conf]
- Abdoul Rjoub, Odysseas G. Koufopavlou
Low voltage swing gates for low power consumption. [Citation Graph (0, 0)][DBLP] ISCAS (1), 1999, pp:234-237 [Conf]
- Nikolaos D. Zervas, Kostas Masselos, Odysseas G. Koufopavlou, Constantinos E. Goutis
Power exploration of multimedia applications realized on embedded cores. [Citation Graph (0, 0)][DBLP] ISCAS (4), 1999, pp:378-381 [Conf]
- Alexander Chatzigeorgiou, Spiridon Nikolaidis, Ioannis Tsoukalas, Odysseas G. Koufopavlou
CMOS gate modeling based on equivalent inverter. [Citation Graph (0, 0)][DBLP] ISCAS (6), 1999, pp:234-237 [Conf]
- Nick A. Moldovyan, Ma A. Eremeev, Nicolas Sklavos, Odysseas G. Koufopavlou
New class of the FPGA efficient cryptographic primitives. [Citation Graph (0, 0)][DBLP] ISCAS (2), 2004, pp:553-556 [Conf]
- Paris Kitsos, Odysseas G. Koufopavlou
Whirlpool hash function: architecture and VLSI implementation. [Citation Graph (0, 0)][DBLP] ISCAS (2), 2004, pp:893-896 [Conf]
- Apostolos P. Fournaris, Odysseas G. Koufopavlou
GF(2/sup K/) multipliers based on Montgomery Multiplication Algorithm. [Citation Graph (0, 0)][DBLP] ISCAS (2), 2004, pp:849-852 [Conf]
- Paris Kitsos, Michalis D. Galanis, Odysseas G. Koufopavlou
High-speed hardware implementations of the KASUMI block cipher. [Citation Graph (0, 0)][DBLP] ISCAS (2), 2004, pp:549-552 [Conf]
- Nicolas Sklavos, Paris Kitsos, K. Papadomanolakis, Odysseas G. Koufopavlou
Random number generator architecture and VLSI implementation. [Citation Graph (0, 0)][DBLP] ISCAS (4), 2002, pp:854-857 [Conf]
- Labros Bisdounis, Odysseas G. Koufopavlou, Spiridon Nikolaidis
Accurate evaluation of CMOS short-circuit power dissipation for short-channel devices. [Citation Graph (0, 0)][DBLP] ISLPED, 1996, pp:189-192 [Conf]
- Nicolas Sklavos, Alexander A. Moldovyan, Odysseas G. Koufopavlou
Encryption and Data Dependent Permutations: Implementation Cost and Performance Evaluation. [Citation Graph (0, 0)][DBLP] MMM-ACNS, 2003, pp:337-348 [Conf]
- Odysseas G. Koufopavlou, George N. Selimis, Nicolas Sklavos, Paris Kitsos
Cryptography: Circuits and Systems Approach. [Citation Graph (0, 0)][DBLP] PATMOS, 2005, pp:750- [Conf]
- Nicolas Sklavos, Odysseas G. Koufopavlou
Architectures and FPGA Implementations of the SCO(-1, -2, -3) Ciphers Family. [Citation Graph (0, 0)][DBLP] VLSI-SOC, 2003, pp:68-73 [Conf]
- Nicolas Sklavos, Odysseas G. Koufopavlou
Data dependent rotations, a trustworthy approach for future encryption systems/ciphers: low cost and high performance. [Citation Graph (0, 0)][DBLP] Computers & Security, 2003, v:22, n:7, pp:585-588 [Journal]
- Nick A. Moldovyan, Nicolas Sklavos, Odysseas G. Koufopavlou
Pure DDP-Based Cipher: Architecture Analysis, Hardware Implementation Cost and Performance up to 6.5 Gbps. [Citation Graph (0, 0)][DBLP] Int. Arab J. Inf. Technol., 2005, v:2, n:1, pp:24-32 [Journal]
- Nicolas Sklavos, Epaminondas Alexopoulos, Odysseas G. Koufopavlou
Networking Data Integrity: High Speed Architectures and Hardware Implementations. [Citation Graph (0, 0)][DBLP] Int. Arab J. Inf. Technol., 2003, v:1, n:0, pp:- [Journal]
- Paris Kitsos, Odysseas G. Koufopavlou
Configurable Hardware Implementations of Bulk Encryption Units for Wireless Communications. [Citation Graph (0, 0)][DBLP] Int. Arab J. Inf. Technol., 2004, v:1, n:1, pp:- [Journal]
- Nicolas Sklavos, Nick A. Moldovyan, Vladimir Gorodetsky, Odysseas G. Koufopavlou
Computer Network Security: Report from MMM-ACNS. [Citation Graph (0, 0)][DBLP] IEEE Security & Privacy, 2004, v:2, n:1, pp:49-52 [Journal]
- Abdoul Rjoub, Odysseas G. Koufopavlou
Multithreshold voltage low-swing/low-voltage techniques in logic gates. [Citation Graph (0, 0)][DBLP] Integration, 2004, v:38, n:2, pp:283-298 [Journal]
- Odysseas G. Koufopavlou, Constantinos E. Goutis
Image reconstruction on a special purpose array processor. [Citation Graph (0, 0)][DBLP] Image Vision Comput., 1992, v:10, n:7, pp:479-484 [Journal]
- Paris Kitsos, Michalis D. Galanis, Odysseas G. Koufopavlou
An Fpga Implementation of the Gprs Encryption Algorithm 3 (gea3). [Citation Graph (0, 0)][DBLP] Journal of Circuits, Systems, and Computers, 2005, v:14, n:2, pp:217-232 [Journal]
- Abdoul Rjoub, M. Alrousan, O. Aljarrah, Odysseas G. Koufopavlou
An Efficient Low-Swing Multithreshold-Voltage Low-Power Design Technique. [Citation Graph (0, 0)][DBLP] Journal of Circuits, Systems, and Computers, 2004, v:13, n:1, pp:193-203 [Journal]
- Nicolas Sklavos, Nick A. Moldovyan, Odysseas G. Koufopavlou
High Speed Networking Security: Design and Implementation of Two New DDP-Based Ciphers. [Citation Graph (0, 0)][DBLP] MONET, 2005, v:10, n:1-2, pp:219-231 [Journal]
- Nicolas Sklavos, Odysseas G. Koufopavlou
Architectures and VLSI Implementations of the AES-Proposal Rijndael. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 2002, v:51, n:12, pp:1454-1459 [Journal]
- Nicolas Sklavos, Paris Kitsos, K. Papadopoulos, Odysseas G. Koufopavlou
Design, Architecture and Performance Evaluation of the Wireless Transport Layer Security. [Citation Graph (0, 0)][DBLP] The Journal of Supercomputing, 2006, v:36, n:1, pp:33-50 [Journal]
- Afxendios Tychopoulos, Odysseas G. Koufopavlou
Optimization of the "FOCUS" Inband-FEC architecture for 10-Gbps SDH/SONET optical communication channels. [Citation Graph (0, 0)][DBLP] DATE, 2007, pp:1575-1580 [Conf]
- Nikolaos Efthymiopoulos, Athanasios Christakidis, Spyros G. Denazis, Odysseas G. Koufopavlou
Enabling Locality in a Balanced Peer-to-Peer Overlay. [Citation Graph (0, 0)][DBLP] GLOBECOM, 2006, pp:- [Conf]
- Paris Kitsos, George Theodoridis, Odysseas G. Koufopavlou
An efficient reconfigurable multiplier architecture for Galois field GF(2m). [Citation Graph (0, 0)][DBLP] Microelectronics Journal, 2003, v:34, n:10, pp:975-980 [Journal]
- Nicolas Sklavos, Odysseas G. Koufopavlou
On the hardware implementation of RIPEMD processor: Networking high speed hashing, up to 2Gbps. [Citation Graph (0, 0)][DBLP] Computers & Electrical Engineering, 2005, v:31, n:6, pp:361-379 [Journal]
- Abdoul Rjoub, Odysseas G. Koufopavlou
Low power high-speed multithreshold voltage CMOS bus architectures. [Citation Graph (0, 0)][DBLP] Computers & Electrical Engineering, 2004, v:30, n:4, pp:269-280 [Journal]
- Paris Kitsos, Nicolas Sklavos, Michalis D. Galanis, Odysseas G. Koufopavlou
64-bit Block ciphers: hardware implementations and comparison analysis. [Citation Graph (0, 0)][DBLP] Computers & Electrical Engineering, 2004, v:30, n:8, pp:593-604 [Journal]
- Apostolos P. Fournaris, Odysseas G. Koufopavlou
Applying systolic multiplication-inversion architectures based on modified extended Euclidean algorithm for GF(2k) in elliptic curve cryptography. [Citation Graph (0, 0)][DBLP] Computers & Electrical Engineering, 2007, v:33, n:5-6, pp:333-348 [Journal]
A Hardware Implementation of CURUPIRA Block Cipher for Wireless Sensors. [Citation Graph (, )][DBLP]
One Dimensional Systolic Inversion Architecture Based on Modified GF(2^k) Extended Euclidean Algorithm. [Citation Graph (, )][DBLP]
P2P-InfoReflect: Dynamic Locality-Aware and Multi-balanced Overlay for Network Dependent Applications and Services. [Citation Graph (, )][DBLP]
A low-power and high-throughput implementation of the SHA-1 hash function. [Citation Graph (, )][DBLP]
Dynamic Service Deployment using an Ontologybased Description of Devices and Services. [Citation Graph (, )][DBLP]
Security Analysis of SIP Signalling during NASS-IMS bundled Authentication. [Citation Graph (, )][DBLP]
Creating an Elliptic Curve arithmetic unit for use in elliptic curve cryptography. [Citation Graph (, )][DBLP]
NASS-IMS bundled authentication study through core network concepts. [Citation Graph (, )][DBLP]
An optimal low-power/high performance DDP-based Cobra-H64 cipher. [Citation Graph (, )][DBLP]
An FPGA-based implementation of the Pomaranch stream cipher. [Citation Graph (, )][DBLP]
AAA and mobile networks: security aspects and architectural efficiency. [Citation Graph (, )][DBLP]
On the architecture and the design of P2P live streaming system schedulers. [Citation Graph (, )][DBLP]
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