Search the dblp DataBase

Publications of Author

1. Aviral Shrivastava, Ilya Issenin, Nikil Dutt
   Compilation techniques for energy reduction in horizontally partitioned cache architectures. [Citation Graph (0, 0)][DBLP]
   CASES, 2005, pp:90-96 [Conf]
   
2. Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil Dutt, Nalini Venkatasubramanian
   Mitigating soft error failures for multimedia applications by selective data protection. [Citation Graph (0, 0)][DBLP]
   CASES, 2006, pp:411-420 [Conf]
   
3. Ilya Issenin, Nikil Dutt
   Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications. [Citation Graph (0, 0)][DBLP]
   CODES+ISSS, 2006, pp:294-299 [Conf]
   
4. Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil Dutt
   Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies. [Citation Graph (0, 0)][DBLP]
   DAC, 2006, pp:49-52 [Conf]
   
5. Ana Azevedo, Ilya Issenin, Radu Cornea, Rajesh Gupta, Nikil D. Dutt, Alexander V. Veidenbaum, Alexandru Nicolau
   Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints. [Citation Graph (0, 0)][DBLP]
   DATE, 2002, pp:168-175 [Conf]
   
6. Ilya Issenin, Erik Brockmeyer, Miguel Miranda, Nikil Dutt
   Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:202-207 [Conf]
   
7. Ilya Issenin, Nikil D. Dutt
   FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations. [Citation Graph (0, 0)][DBLP]
   DATE, 2005, pp:808-813 [Conf]
   
8. Doosan Cho, Ilya Issenin, Nikil Dutt, Jonghee W. Yoon, Yunheung Paek
   Software controlled memory layout reorganization for irregular array access patterns. [Citation Graph (0, 0)][DBLP]
   CASES, 2007, pp:179-188 [Conf]
   
9. Ilya Issenin, Nikil Dutt
   Data Reuse Driven Memory and Network-On-Chip Co-Synthesis. [Citation Graph (0, 0)][DBLP]
   IESS, 2007, pp:299-312 [Conf]
   
10. Ilya Issenin, Nikil Dutt
    FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
    
11. Ilya Issenin, Erik Brockmeyer, Miguel Miranda, Nikil Dutt
    DRDU: A data reuse analysis technique for efficient scratch-pad memory management. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:2, pp:- [Journal]
    
12. 
    A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures. [Citation Graph (, )][DBLP]
    
    
13. 
    Compiler driven data layout optimization for regular/irregular array access patterns. [Citation Graph (, )][DBLP]