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Yunheung Paek: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jeonghun Cho, Jinhwan Kim, Yunheung Paek
    A Study on Data Allocation of On-Chip Dual Memory Banks. [Citation Graph (0, 0)][DBLP]
    Interaction between Compilers and Computer Architectures, 2002, pp:68-0 [Conf]
  2. Yunheung Paek, Angeles G. Navarro, Emilio L. Zapata, David A. Padua
    Parallelization of Benchmarks for Scalable Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1998, pp:401-0 [Conf]
  3. Sungjoon Jung, Yunheung Paek
    The very portable optimizer for digital signal processors. [Citation Graph (0, 0)][DBLP]
    CASES, 2001, pp:84-92 [Conf]
  4. Jinhwan Kim, Sungjoon Jung, Yunheung Paek, Gang-Ryung Uh
    Experience with a retargetable compiler for a commercial network processor. [Citation Graph (0, 0)][DBLP]
    CASES, 2002, pp:178-187 [Conf]
  5. Sang Seok Lim, Yunheung Paek, Kyu Ho Park, Jay Hoeflinger
    A Parallel Programming Environment for a V-Busbased PC-cluste. [Citation Graph (0, 0)][DBLP]
    CLUSTER, 2001, pp:235-0 [Conf]
  6. Minwook Ahn, Jonghee W. Yoon, Yunheung Paek, Yoonjin Kim, Mary Kiemb, Kiyoung Choi
    A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:363-368 [Conf]
  7. Sanghyun Park, Eugene Earlie, Aviral Shrivastava, Alex Nicolau, Nikil Dutt, Yunheung Paek
    Automatic generation of operation tables for fast exploration of bypasses in embedded processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1197-1202 [Conf]
  8. Jeonghun Cho, Yunheung Paek
    Run-Time Memory Optimization for DDMB Architecture Through a CCB Algorithm. [Citation Graph (0, 0)][DBLP]
    EUC Workshops, 2006, pp:775-784 [Conf]
  9. Doosan Cho, Ravi Ayyagari, Gang-Ryung Uh, Yunheung Paek
    Instruction Re-selection for Iterative Modulo Scheduling on High Performance Multi-issue DSPs. [Citation Graph (0, 0)][DBLP]
    EUC Workshops, 2006, pp:741-754 [Conf]
  10. Andrew Sohn, Yunheung Paek, Jui-Yuan Ku, Yuetsu Kodama, Yoshinori Yamaguchi
    Communication Studies of Single-Threaded and Multithreaded Distributed-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:310-314 [Conf]
  11. William Blume, Rudolf Eigenmann, Keith Faigin, John Grout, Jaejin Lee, Thomas Lawrence, Jay Hoeflinger, David A. Padua, Yunheung Paek, Paul Petersen, William M. Pottenger, Lawrence Rauchwerger, Peng Tu, Stephen Weatherford
    Restructuring Programs for High-Speed Computers with Polaris. [Citation Graph (0, 0)][DBLP]
    ICPP Workshop, 1996, pp:149-161 [Conf]
  12. Sejong Oh, Yunheung Paek
    A Quantitative Comparison of Two Retargetable Compilation Approaches. [Citation Graph (0, 0)][DBLP]
    ICPP, 2003, pp:29-0 [Conf]
  13. Angeles G. Navarro, Emilio L. Zapata, Yunheung Paek, David A. Padua
    Compiler Techniques for Effective Communication on Distributed-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP, 1997, pp:74-77 [Conf]
  14. Yunheung Paek, David A. Padua
    Experimental Study of Compiler Techniques for NUMA Machines. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1998, pp:187-193 [Conf]
  15. Yoonjin Kim, Ilhyun Park, Kiyoung Choi, Yunheung Paek
    Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:310-315 [Conf]
  16. Jay Hoeflinger, Yunheung Paek
    A Comparative Analysis of Dependence Testing Mechanisms. [Citation Graph (0, 0)][DBLP]
    LCPC, 2000, pp:289-303 [Conf]
  17. Jay Hoeflinger, Yunheung Paek
    The Access Region Test. [Citation Graph (0, 0)][DBLP]
    LCPC, 1999, pp:271-285 [Conf]
  18. Yunheung Paek, Junsik Choi, Jinoo Joung, Junseo Lee, Seonwook Kim
    Exploiting Parallelism in Memory Operations for Code Optimization. [Citation Graph (0, 0)][DBLP]
    LCPC, 2004, pp:132-148 [Conf]
  19. Yunheung Paek, David A. Padua
    Automatic Parallelization for Non-cache Coherent Multiprocessors. [Citation Graph (0, 0)][DBLP]
    LCPC, 1996, pp:266-284 [Conf]
  20. Jeonghun Cho, Yunheung Paek, David B. Whalley
    Efficient register and memory assignment for non-orthogonal architectures via graph coloring and MST algorithms. [Citation Graph (0, 0)][DBLP]
    LCTES-SCOPES, 2002, pp:130-138 [Conf]
  21. Prasad Kulkarni, Wankang Zhao, Hwashin Moon, Kyunghwan Cho, David B. Whalley, Jack W. Davidson, Mark W. Bailey, Yunheung Paek, Kyle Gallivan
    Finding effective optimization phase sequences. [Citation Graph (0, 0)][DBLP]
    LCTES, 2003, pp:12-23 [Conf]
  22. Sanghyun Park, Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek, Eugene Earlie
    Bypass aware instruction scheduling for register file power reduction. [Citation Graph (0, 0)][DBLP]
    LCTES, 2006, pp:173-181 [Conf]
  23. Yunheung Paek, Jay Hoeflinger, David A. Padua
    Simplification of Array Access Patterns for Compiler Optimizations. [Citation Graph (0, 0)][DBLP]
    PLDI, 1998, pp:60-71 [Conf]
  24. Yunheung Paek, Minwook Ahn, Soonho Lee
    Case Studies on Automatic Extraction of Target-Specific Architectural Parameters in Complex Code Generation. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:151-166 [Conf]
  25. William Blume, Ramon Doallo, Rudolf Eigenmann, John Grout, Jay Hoeflinger, Thomas Lawrence, Jaejin Lee, David A. Padua, Yunheung Paek, William M. Pottenger, Lawrence Rauchwerger, Peng Tu
    Parallel Programming with Polaris. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1996, v:29, n:12, pp:87-81 [Journal]
  26. Jay Hoeflinger, Yunheung Paek, Kwang Yi
    Unified Interprocedural Parallelism Detection. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2001, v:29, n:2, pp:185-215 [Journal]
  27. Oukseh Lee, Kwangkeun Yi, Yunheung Paek
    A proof method for the correctness of modularized 0CFA. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 2002, v:81, n:4, pp:179-185 [Journal]
  28. Yunheung Paek, David A. Padua
    Compiling for Scalable Multiprocessors with Polaris. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1997, v:7, n:4, pp:425-436 [Journal]
  29. Jinhwan Kim, Yunheung Paek, Gang-Ryung Uh
    Code optimizations for a VLIW-style network processing unit. [Citation Graph (0, 0)][DBLP]
    Softw., Pract. Exper., 2004, v:34, n:9, pp:847-874 [Journal]
  30. Gang-Ryung Uh, Yuhong Wang, David B. Whalley, Sanjay Jinturkar, Yunheung Paek, Vincent Cao, Chris Burns
    Compiler transformations for effectively exploiting a zero overhead loop buffer. [Citation Graph (0, 0)][DBLP]
    Softw., Pract. Exper., 2005, v:35, n:4, pp:393-412 [Journal]
  31. Prasad Kulkarni, Wankang Zhao, Stephen Hines, David B. Whalley, Xin Yuan, Robert van Engelen, Kyle Gallivan, Jason Hiser, Jack W. Davidson, Baosheng Cai, Mark W. Bailey, Hwashin Moon, Kyunghwan Cho, Yunheung Paek
    VISTA: VPO interactive system for tuning applications. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:4, pp:819-863 [Journal]
  32. Jeonghun Cho, Yunheung Paek, David B. Whalley
    Fast memory bank assignment for fixed-point digital signal processors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2004, v:9, n:1, pp:52-74 [Journal]
  33. Yunheung Paek, Jay Hoeflinger, David A. Padua
    Efficient and precise array access analysis. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 2002, v:24, n:1, pp:65-109 [Journal]
  34. Yunheung Paek, Angeles G. Navarro, Emilio L. Zapata, Jay Hoeflinger, David A. Padua
    An Advanced Compiler Framework for Non-Cache-Coherent Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2002, v:13, n:3, pp:241-259 [Journal]
  35. Doosan Cho, Ilya Issenin, Nikil Dutt, Jonghee W. Yoon, Yunheung Paek
    Software controlled memory layout reorganization for irregular array access patterns. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:179-188 [Conf]
  36. Doosan Cho, Ravi Ayyagari, Gang-Ryung Uh, Yunheung Paek
    Preprocessing Strategy for Effective Modulo Scheduling on Multi-issue Digital Signal Processors. [Citation Graph (0, 0)][DBLP]
    CC, 2007, pp:16-31 [Conf]
  37. Minwook Ahn, Jooyeon Lee, Yunheung Paek
    Optimistic coalescing for heterogeneous register architectures. [Citation Graph (0, 0)][DBLP]
    LCTES, 2007, pp:93-102 [Conf]
  38. Rajiv Gupta, Yunheung Paek
    Introduction to the special LCTES'05 issue. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2007, v:6, n:4, pp:- [Journal]

  39. SPKM : A novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures. [Citation Graph (, )][DBLP]


  40. A code-generator generator for multi-output instructions. [Citation Graph (, )][DBLP]


  41. Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors. [Citation Graph (, )][DBLP]


  42. Iterative Algorithm for Compound Instruction Selection with Register Coalescing. [Citation Graph (, )][DBLP]


  43. Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays. [Citation Graph (, )][DBLP]


  44. Orthogonal Instruction Encoding for a 16-bit Embedded Processor with Dynamic Implied Addressing Mode. [Citation Graph (, )][DBLP]


  45. Compiler driven data layout optimization for regular/irregular array access patterns. [Citation Graph (, )][DBLP]


  46. Operation and data mapping for CGRAs with multi-bank memory. [Citation Graph (, )][DBLP]


  47. A new addressing mode for the encoding space problem on embedded processors. [Citation Graph (, )][DBLP]


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