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Yuh-Fang Tsai: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Lin Li, Ismail Kadayif, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Anand Sivasubramaniam
    Leakage Energy Management in Cache Hierarchies. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2002, pp:131-140 [Conf]
  2. David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mary Jane Irwin
    Evaluating Run-Time Techniques for Leakage Power Reduction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:31-38 [Conf]
  3. Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin
    Implications of technology scaling on leakage reduction techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:187-190 [Conf]
  4. Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
    Leakage-Aware Interconnect for On-Chip Network. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:230-231 [Conf]
  5. Aman Gayasen, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan
    Reducing leakage energy in FPGAs using region-constrained placement. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:51-58 [Conf]
  6. Yuh-Fang Tsai, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
    Three-Dimensional Cache Design Exploration Using 3DCacti. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:519-524 [Conf]
  7. Wei Zhang 0002, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, David Duarte, Yuh-Fang Tsai
    Exploiting VLIW schedule slacks for dynamic and leakage energy reduction. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:102-113 [Conf]
  8. David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mary Jane Irwin
    Evaluating Run-Time Techniques for Leakage Power Reduction. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:31-38 [Conf]
  9. Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
    Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:374-379 [Conf]
  10. Lin Li, Ismail Kadayif, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Anand Sivasubramaniam
    Managing Leakage Energy in Cache Hierarchies. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2003, v:5, n:, pp:- [Journal]
  11. Wei Zhang 0002, Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Reducing dynamic and leakage energy in VLIW architectures. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:1, pp:1-28 [Journal]
  12. Yuh-Fang Tsai, D. E. Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin
    Characterization and modeling of run-time techniques for leakage power reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:11, pp:1221-1233 [Journal]
  13. Yuh-Fang Tsai, Vijaykrishnan Narayaynan, Yuan Xie, Mary Jane Irwin
    Leakage-Aware Interconnect for On-Chip Network [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

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