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Abhik Roychoudhury: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Tulika Mitra, Abhik Roychoudhury, Qinghua Shen
    Impact of Java Memory Model on Out-of-Order Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2004, pp:99-110 [Conf]
  2. Abhik Roychoudhury, P. S. Thiagarajan
    Communicating Transaction Processes: An MSC-Based Model of Computation for Reactive Embedded Systems. [Citation Graph (0, 0)][DBLP]
    Lectures on Concurrency and Petri Nets, 2003, pp:789-818 [Conf]
  3. Abhik Roychoudhury, P. S. Thiagarajan
    Communicating Transaction Processes. [Citation Graph (0, 0)][DBLP]
    ACSD, 2003, pp:157-166 [Conf]
  4. Abhik Roychoudhury, K. Narayan Kumar, C. R. Ramakrishnan, I. V. Ramakrishnan
    Beyond Tamaki-Sato Style Unfold/Fold Transformations for Normal Logic Programs. [Citation Graph (0, 0)][DBLP]
    ASIAN, 1999, pp:322-333 [Conf]
  5. Amy P. Felty, Douglas J. Howe, Abhik Roychoudhury
    Formal Metatheory using Implicit Syntax, and an Application to Data Abstraction for Asynchronous Systems. [Citation Graph (0, 0)][DBLP]
    CADE, 1999, pp:237-251 [Conf]
  6. C. R. Ramakrishnan, I. V. Ramakrishnan, Scott A. Smolka, Yifei Dong, Xiaoqun Du, Abhik Roychoudhury, V. N. Venkatakrishnan
    XMC: A Logic-Programming-Based Verification Toolset. [Citation Graph (0, 0)][DBLP]
    CAV, 2000, pp:576-580 [Conf]
  7. Abhik Roychoudhury, I. V. Ramakrishnan
    Automated Inductive Verification of Parameterized Protocols. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:25-37 [Conf]
  8. Liang Guo, Abhik Roychoudhury, Tao Wang
    Accurately Choosing Execution Runs for Software Fault Localization. [Citation Graph (0, 0)][DBLP]
    CC, 2006, pp:80-95 [Conf]
  9. Hemendra Singh Negi, Tulika Mitra, Abhik Roychoudhury
    Accurate estimation of cache-related preemption delay. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:201-206 [Conf]
  10. Xianfeng Li, Tulika Mitra, Abhik Roychoudhury
    Accurate timing analysis by modeling caches, speculation and their interaction. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:466-471 [Conf]
  11. Vivy Suhendra, Tulika Mitra, Abhik Roychoudhury, Ting Chen
    Efficient detection and exploitation of infeasible paths for software timing analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:358-363 [Conf]
  12. Abhik Roychoudhury, Tulika Mitra, S. R. Karri
    Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10828-10833 [Conf]
  13. Thuan Quang Huynh, Abhik Roychoudhury
    A Memory Model Sensitive Checker for C#. [Citation Graph (0, 0)][DBLP]
    FM, 2006, pp:476-491 [Conf]
  14. Abhik Roychoudhury, Susmita Sur-Kolay
    Efficient Algorithms for Vertex Arboricity of Planar Graphs. [Citation Graph (0, 0)][DBLP]
    FSTTCS, 1995, pp:37-51 [Conf]
  15. Abhik Roychoudhury, C. R. Ramakrishnan, I. V. Ramakrishnan, R. C. Sekar
    A Conservative Technique to Improve Deterministic Evaluation of Logic Programs. [Citation Graph (0, 0)][DBLP]
    ICCL, 1998, pp:196-205 [Conf]
  16. Abhik Roychoudhury, Tulika Mitra, Hemendra Singh Negi
    Analyzing Loop Paths for Execution Time Estimation. [Citation Graph (0, 0)][DBLP]
    ICDCIT, 2005, pp:458-469 [Conf]
  17. Abhik Roychoudhury
    Formal Reasoning about Hardware and Software Memory Models. [Citation Graph (0, 0)][DBLP]
    ICFEM, 2002, pp:423-434 [Conf]
  18. Abhik Roychoudhury, K. Narayan Kumar, I. V. Ramakrishnan
    Generalized Unfold/fold Transformation Systems for Normal Logic Programs. [Citation Graph (0, 0)][DBLP]
    ICLP, 1999, pp:616- [Conf]
  19. Xianfeng Li, Hemendra Singh Negi, Tulika Mitra, Abhik Roychoudhury
    Design space exploration of caches using compressed traces. [Citation Graph (0, 0)][DBLP]
    ICS, 2004, pp:116-125 [Conf]
  20. Ankit Goel, Sun Meng, Abhik Roychoudhury, P. S. Thiagarajan
    Interacting process classes. [Citation Graph (0, 0)][DBLP]
    ICSE, 2006, pp:302-311 [Conf]
  21. Abhik Roychoudhury, Tulika Mitra
    Specifying multithreaded Java semantics for program verification. [Citation Graph (0, 0)][DBLP]
    ICSE, 2002, pp:489-499 [Conf]
  22. Tao Wang, Abhik Roychoudhury
    Using Compressed Bytecode Traces for Slicing Java Programs. [Citation Graph (0, 0)][DBLP]
    ICSE, 2004, pp:512-521 [Conf]
  23. Abhik Roychoudhury, Xianfeng Li, Tulika Mitra
    Timing Analysis of Embedded Software for Speculative Processors. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:126-131 [Conf]
  24. Abhik Roychoudhury
    Depiction and Playout of Multi-threaded Program Executions. [Citation Graph (0, 0)][DBLP]
    ASE, 2003, pp:331-336 [Conf]
  25. Tao Wang, Abhik Roychoudhury
    Automated path generation for software fault localization. [Citation Graph (0, 0)][DBLP]
    ASE, 2005, pp:347-351 [Conf]
  26. Abhik Roychoudhury, C. R. Ramakrishnan
    Unfold/Fold Transformations for Automated Verification of Parameterized Concurrent Systems. [Citation Graph (0, 0)][DBLP]
    Program Development in Computational Logic, 2004, pp:261-290 [Conf]
  27. Tao Wang, Abhik Roychoudhury, Roland H. C. Yap, S. C. Choudhary
    Symbolic Execution of Behavioral Requirements. [Citation Graph (0, 0)][DBLP]
    PADL, 2004, pp:178-192 [Conf]
  28. Baoqiu Cui, Yifei Dong, Xiaoqun Du, K. Narayan Kumar, C. R. Ramakrishnan, I. V. Ramakrishnan, Abhik Roychoudhury, Scott A. Smolka, David Scott Warren
    Logic Programming and Model Checking. [Citation Graph (0, 0)][DBLP]
    PLILP/ALP, 1998, pp:1-20 [Conf]
  29. Abhik Roychoudhury, K. Narayan Kumar, C. R. Ramakrishnan, I. V. Ramakrishnan
    A Parameterized Unfold/Fold Transformation Framework for Definite Logic Programs. [Citation Graph (0, 0)][DBLP]
    PPDP, 1999, pp:396-413 [Conf]
  30. Abhik Roychoudhury, C. R. Ramakrishnan, I. V. Ramakrishnan
    Justifying proofs using memo tables. [Citation Graph (0, 0)][DBLP]
    PPDP, 2000, pp:178-189 [Conf]
  31. Ankit Goel, Abhik Roychoudhury, Tulika Mitra
    Compactly representing parallel program executions. [Citation Graph (0, 0)][DBLP]
    PPOPP, 2003, pp:191-202 [Conf]
  32. Xianfeng Li, Abhik Roychoudhury, Tulika Mitra
    Modeling Out-of-Order Processors for Software Timing Analysis. [Citation Graph (0, 0)][DBLP]
    RTSS, 2004, pp:92-103 [Conf]
  33. Abhik Roychoudhury, P. S. Thiagarajan, Tuan-Anh Tran, Vera A. Zvereva
    Automatic Generation of Protocol Converters from Scenario-Based Specifications. [Citation Graph (0, 0)][DBLP]
    RTSS, 2004, pp:447-458 [Conf]
  34. Vivy Suhendra, Tulika Mitra, Abhik Roychoudhury, Ting Chen
    WCET Centric Data Allocation to Scratchpad Memory. [Citation Graph (0, 0)][DBLP]
    RTSS, 2005, pp:223-232 [Conf]
  35. Abhik Roychoudhury, K. Narayan Kumar, C. R. Ramakrishnan, I. V. Ramakrishnan, Scott A. Smolka
    Verification of Parameterized Systems Using Logic Program Transformations. [Citation Graph (0, 0)][DBLP]
    TACAS, 2000, pp:172-187 [Conf]
  36. Abhik Roychoudhury, C. R. Ramakrishnan, I. V. Ramakrishnan, Scott A. Smolka
    Tabulation-based Induction Proofs with Application to Automated Verification. [Citation Graph (0, 0)][DBLP]
    TAPD, 1998, pp:83-88 [Conf]
  37. Abhik Roychoudhury, P. S. Thiagarajan
    An Executable Specification Language Based on Message Sequence Charts. [Citation Graph (0, 0)][DBLP]
    10th Anniversary Colloquium of UNU/IIST, 2002, pp:226-241 [Conf]
  38. Biman Chakraborty, Ting Chen, Tulika Mitra, Abhik Roychoudhury
    Handling Constraints in Multi-Objective GA for Embedded System Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:305-310 [Conf]
  39. Samarjit Chakraborty, Abhik Roychoudhury
    Tutorial T8B: Performance Debugging of Complex Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:13- [Conf]
  40. Abhik Roychoudhury, I. V. Ramakrishnan
    Inductively Verifying Invariant Properties of Parameterized Systems. [Citation Graph (0, 0)][DBLP]
    Autom. Softw. Eng., 2004, v:11, n:2, pp:101-139 [Journal]
  41. Sandro Etalle, Supratik Mukhopadhyay, Abhik Roychoudhury
    Preface. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2005, v:118, n:, pp:1-0 [Journal]
  42. Supratik Mukhopadhyay, Abhik Roychoudhury, Zijiang Yang
    Preface. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2006, v:157, n:1, pp:1- [Journal]
  43. Abhik Roychoudhury, K. Narayan Kumar, C. R. Ramakrishnan, I. V. Ramakrishnan
    Beyond Tamaki-Sato Style Unfold/Fold Transformations for Normal Logic Programs. [Citation Graph (0, 0)][DBLP]
    Int. J. Found. Comput. Sci., 2002, v:13, n:3, pp:387-403 [Journal]
  44. Xianfeng Li, Tulika Mitra, Abhik Roychoudhury
    Modeling Control Speculation for Timing Analysis. [Citation Graph (0, 0)][DBLP]
    Real-Time Systems, 2005, v:29, n:1, pp:27-58 [Journal]
  45. Xianfeng Li, Abhik Roychoudhury, Tulika Mitra
    Modeling out-of-order processors for WCET analysis. [Citation Graph (0, 0)][DBLP]
    Real-Time Systems, 2006, v:34, n:3, pp:195-227 [Journal]
  46. Abhik Roychoudhury, K. Narayan Kumar, C. R. Ramakrishnan, I. V. Ramakrishnan
    An unfold/fold transformation framework for definite logic programs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 2004, v:26, n:3, pp:464-509 [Journal]
  47. Lei Ju, Samarjit Chakraborty, Abhik Roychoudhury
    Accounting for cache-related preemption delay in dynamic priority schedulability analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1623-1628 [Conf]
  48. Tao Wang, Abhik Roychoudhury
    Hierarchical dynamic slicing. [Citation Graph (0, 0)][DBLP]
    ISSTA, 2007, pp:228-238 [Conf]
  49. Abhik Roychoudhury, Ankit Goel, Bikram Sengupta
    Symbolic message sequence charts. [Citation Graph (0, 0)][DBLP]
    ESEC/SIGSOFT FSE, 2007, pp:275-284 [Conf]

  50. A Retargetable Software Timing Analyzer Using Architecture Description Language. [Citation Graph (, )][DBLP]


  51. Cache-aware optimization of BAN applications. [Citation Graph (, )][DBLP]


  52. Scratchpad allocation for concurrent embedded software. [Citation Graph (, )][DBLP]


  53. Performance debugging of Esterel specifications. [Citation Graph (, )][DBLP]


  54. Generating test programs to cover pipeline interactions. [Citation Graph (, )][DBLP]


  55. Context-sensitive timing analysis of Esterel programs. [Citation Graph (, )][DBLP]


  56. Timing analysis of esterel programs on general-purpose multiprocessors. [Citation Graph (, )][DBLP]


  57. Cache-Aware Timing Analysis of Streaming Applications. [Citation Graph (, )][DBLP]


  58. Fair Model Checking with Process Counter Abstraction. [Citation Graph (, )][DBLP]


  59. Footprinter: Round-trip engineering via scenario and state based models. [Citation Graph (, )][DBLP]


  60. Debugging Statecharts Via Model-Code Traceability. [Citation Graph (, )][DBLP]


  61. Synthesis and Traceability of Scenario-Based Executable Models. [Citation Graph (, )][DBLP]


  62. Test generation to expose changes in evolving programs. [Citation Graph (, )][DBLP]


  63. Java memory model aware software validation. [Citation Graph (, )][DBLP]


  64. Schedulability Analysis of MSC-based System Models. [Citation Graph (, )][DBLP]


  65. Unified Cache Modeling for WCET Analysis and Layout Optimizations. [Citation Graph (, )][DBLP]


  66. Timing Analysis of Concurrent Programs Running on Shared Cache Multi-Cores. [Citation Graph (, )][DBLP]


  67. Darwin: an approach for debugging evolving programs. [Citation Graph (, )][DBLP]


  68. Exploiting Branch Constraints without Exhaustive Path Enumeration. [Citation Graph (, )][DBLP]


  69. Timing Analysis of Body Area Network Applications. [Citation Graph (, )][DBLP]


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