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Tulika Mitra: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Tulika Mitra, Abhik Roychoudhury, Qinghua Shen
    Impact of Java Memory Model on Out-of-Order Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2004, pp:99-110 [Conf]
  2. Pan Yu, Tulika Mitra
    Scalable custom instructions identification for instruction-set extensible processors. [Citation Graph (0, 0)][DBLP]
    CASES, 2004, pp:69-78 [Conf]
  3. Vivy Suhendra, Chandrashekar Raghavan, Tulika Mitra
    Integrated scratchpad memory optimization and task scheduling for MPSoC architectures. [Citation Graph (0, 0)][DBLP]
    CASES, 2006, pp:401-410 [Conf]
  4. Pan Yu, Tulika Mitra
    Satisfying real-time constraints with custom instructions. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:166-171 [Conf]
  5. Hemendra Singh Negi, Tulika Mitra, Abhik Roychoudhury
    Accurate estimation of cache-related preemption delay. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:201-206 [Conf]
  6. Ramkumar Jayaseelan, Haibin Liu, Tulika Mitra
    Exploiting forwarding to improve data bandwidth of instruction-set extensions. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:43-48 [Conf]
  7. Xianfeng Li, Tulika Mitra, Abhik Roychoudhury
    Accurate timing analysis by modeling caches, speculation and their interaction. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:466-471 [Conf]
  8. Pan Yu, Tulika Mitra
    Characterizing embedded applications for instruction-set extensible processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:723-728 [Conf]
  9. Vivy Suhendra, Tulika Mitra, Abhik Roychoudhury, Ting Chen
    Efficient detection and exploitation of infeasible paths for software timing analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:358-363 [Conf]
  10. Abhik Roychoudhury, Tulika Mitra, S. R. Karri
    Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10828-10833 [Conf]
  11. Tulika Mitra, Tzi-cker Chiueh
    Compression-Domain Editing of 3D Models. [Citation Graph (0, 0)][DBLP]
    DCC, 2003, pp:343-352 [Conf]
  12. Tulika Mitra, Tzi-cker Chiueh
    An FPGA Implementation of Triangle Mesh Decompression. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:22-0 [Conf]
  13. Jirong Liao, Weng-Fai Wong, Tulika Mitra
    A Model for Hardware Realization of Kernel Loops. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:334-344 [Conf]
  14. Lei He, Tulika Mitra, Weng-Fai Wong
    Configuration bitstream compression for dynamically reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:766-773 [Conf]
  15. Abhik Roychoudhury, Tulika Mitra, Hemendra Singh Negi
    Analyzing Loop Paths for Execution Time Estimation. [Citation Graph (0, 0)][DBLP]
    ICDCIT, 2005, pp:458-469 [Conf]
  16. Tulika Mitra, Chuan-Kai Yang, Tzi-cker Chiueh
    Application-Specific File Prefetching for Multimedia Programs. [Citation Graph (0, 0)][DBLP]
    IEEE International Conference on Multimedia and Expo (I), 2000, pp:459-462 [Conf]
  17. Tulika Mitra, Tzi-cker Chiueh
    Implementation and Evaluation of the Parallel Mesa Library. [Citation Graph (0, 0)][DBLP]
    ICPADS, 1998, pp:84-91 [Conf]
  18. Xianfeng Li, Hemendra Singh Negi, Tulika Mitra, Abhik Roychoudhury
    Design space exploration of caches using compressed traces. [Citation Graph (0, 0)][DBLP]
    ICS, 2004, pp:116-125 [Conf]
  19. Abhik Roychoudhury, Tulika Mitra
    Specifying multithreaded Java semantics for program verification. [Citation Graph (0, 0)][DBLP]
    ICSE, 2002, pp:489-499 [Conf]
  20. Tulika Mitra, Tzi-cker Chiueh
    Compression-Domain Parallel Rendering. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  21. Sriram Vajapeyam, P. J. Joseph, Tulika Mitra
    Dynamic Vectorization: A Mechanism for Exploiting Far-Flung ILP in Ordinary Programs. [Citation Graph (0, 0)][DBLP]
    ISCA, 1999, pp:16-27 [Conf]
  22. Sriram Vajapeyam, Tulika Mitra
    Improving Superscalar Instruction Dispatch and Issue by Exploiting Dynamic Code Sequences. [Citation Graph (0, 0)][DBLP]
    ISCA, 1997, pp:1-12 [Conf]
  23. Abhik Roychoudhury, Xianfeng Li, Tulika Mitra
    Timing Analysis of Embedded Software for Speculative Processors. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:126-131 [Conf]
  24. Tulika Mitra, Tzi-cker Chiueh
    Dynamic 3D Graphics Workload Characterization and the Architectural Implications. [Citation Graph (0, 0)][DBLP]
    MICRO, 1999, pp:62-71 [Conf]
  25. Tzi-cker Chiueh, Tulika Mitra, Anindya Neogi, Chuan-Kai Yang
    Zodiac: A History-Based Interactive Video Authoring System. [Citation Graph (0, 0)][DBLP]
    ACM Multimedia, 1998, pp:435-444 [Conf]
  26. Ankit Goel, Abhik Roychoudhury, Tulika Mitra
    Compactly representing parallel program executions. [Citation Graph (0, 0)][DBLP]
    PPOPP, 2003, pp:191-202 [Conf]
  27. Ramkumar Jayaseelan, Tulika Mitra, Xianfeng Li
    Estimating the Worst-Case Energy Consumption of Embedded Software. [Citation Graph (0, 0)][DBLP]
    IEEE Real Time Technology and Applications Symposium, 2006, pp:81-90 [Conf]
  28. Xianfeng Li, Abhik Roychoudhury, Tulika Mitra
    Modeling Out-of-Order Processors for Software Timing Analysis. [Citation Graph (0, 0)][DBLP]
    RTSS, 2004, pp:92-103 [Conf]
  29. Vivy Suhendra, Tulika Mitra, Abhik Roychoudhury, Ting Chen
    WCET Centric Data Allocation to Scratchpad Memory. [Citation Graph (0, 0)][DBLP]
    RTSS, 2005, pp:223-232 [Conf]
  30. Chuan-Kai Yang, Tulika Mitra, Tzi-cker Chiueh
    A Decoupled Architecture for Application-Specific File Prefetching. [Citation Graph (0, 0)][DBLP]
    USENIX Annual Technical Conference, FREENIX Track, 2002, pp:157-170 [Conf]
  31. Chuan-Kai Yang, Tulika Mitra, Tzi-cker Chiueh
    On-the-Fly rendering of losslessly compressed irregular volume data. [Citation Graph (0, 0)][DBLP]
    IEEE Visualization, 2000, pp:101-108 [Conf]
  32. Biman Chakraborty, Ting Chen, Tulika Mitra, Abhik Roychoudhury
    Handling Constraints in Multi-Objective GA for Embedded System Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:305-310 [Conf]
  33. Tzi-cker Chiueh, Tulika Mitra, Anindya Neogi, Chuan-Kai Yang
    Zodiac: A history-based interactive video authoring system. [Citation Graph (0, 0)][DBLP]
    Multimedia Syst., 2000, v:8, n:3, pp:201-211 [Journal]
  34. Xianfeng Li, Tulika Mitra, Abhik Roychoudhury
    Modeling Control Speculation for Timing Analysis. [Citation Graph (0, 0)][DBLP]
    Real-Time Systems, 2005, v:29, n:1, pp:27-58 [Journal]
  35. Xianfeng Li, Abhik Roychoudhury, Tulika Mitra
    Modeling out-of-order processors for WCET analysis. [Citation Graph (0, 0)][DBLP]
    Real-Time Systems, 2006, v:34, n:3, pp:195-227 [Journal]
  36. Huynh Phung Huynh, Joon Edward Sim, Tulika Mitra
    An efficient framework for dynamic reconfiguration of instruction-set customization. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:135-144 [Conf]
  37. Huynh Phung Huynh, Tulika Mitra
    Instruction-set customization for real-time embedded systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1472-1477 [Conf]

  38. A Retargetable Software Timing Analyzer Using Architecture Description Language. [Citation Graph (, )][DBLP]

  39. Cache-aware optimization of BAN applications. [Citation Graph (, )][DBLP]

  40. Scratchpad allocation for concurrent embedded software. [Citation Graph (, )][DBLP]

  41. Static analysis for fast and accurate design space exploration of caches. [Citation Graph (, )][DBLP]

  42. Cache modeling in probabilistic execution time analysis. [Citation Graph (, )][DBLP]

  43. Exploring locking & partitioning for predictable shared caches on multi-cores. [Citation Graph (, )][DBLP]

  44. Generating test programs to cover pipeline interactions. [Citation Graph (, )][DBLP]

  45. Evaluating design trade-offs in customizable processors. [Citation Graph (, )][DBLP]

  46. Dynamic thermal management via architectural adaptation. [Citation Graph (, )][DBLP]

  47. A DVS-based pipelined reconfigurable instruction memory. [Citation Graph (, )][DBLP]

  48. Instruction cache locking using temporal reuse profile. [Citation Graph (, )][DBLP]

  49. Runtime reconfiguration of custom instructions for real-time embedded systems. [Citation Graph (, )][DBLP]

  50. Cache-Aware Timing Analysis of Streaming Applications. [Citation Graph (, )][DBLP]

  51. Probabilistic modeling of data cache behavior. [Citation Graph (, )][DBLP]

  52. Disjoint Pattern Enumeration for Custom Instructions Identification. [Citation Graph (, )][DBLP]

  53. Temperature aware task sequencing and voltage scaling. [Citation Graph (, )][DBLP]

  54. A hybrid local-global approach for multi-core thermal management. [Citation Graph (, )][DBLP]

  55. Timing Analysis of Concurrent Programs Running on Shared Cache Multi-Cores. [Citation Graph (, )][DBLP]

  56. Runtime Adaptive Extensible Embedded Processors - A Survey. [Citation Graph (, )][DBLP]

  57. Temperature Aware Scheduling for Embedded Processors. [Citation Graph (, )][DBLP]

  58. Exploiting Branch Constraints without Exhaustive Path Enumeration. [Citation Graph (, )][DBLP]

  59. Timing Analysis of Body Area Network Applications. [Citation Graph (, )][DBLP]

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