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Satnam Singh: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Koen Claessen, Mary Sheeran, Satnam Singh
    The Design and Verification of a Sorter Core. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:355-369 [Conf]
  2. Satnam Singh
    Design and Verification of CoreConnectTM IP Using Esterel. [Citation Graph (0, 0)][DBLP]
    CHARME, 2003, pp:283-288 [Conf]
  3. Satnam Singh
    System Level Specification in Lava. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10370-10375 [Conf]
  4. Satnam Singh
    A Demonstration of Co-Design and Co-Verification in a Synchronous Language. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1394-1395 [Conf]
  5. Donald MacVicar, Satnam Singh, Robert Slous
    Be'zier Curve Rendering on Virtex(tm). [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:314-0 [Conf]
  6. Jim Burns, Adam Donlin, Jonathan Hogg, Satnam Singh, Mark De Wit
    A dynamic reconfiguration run-time system. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:66-76 [Conf]
  7. Nicholas McKay, Thomas F. Melham, Kong Woei Susanto, Satnam Singh
    Dynamic Specialization of XC6200 FPGAs by Partial Evaluation. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:308-309 [Conf]
  8. Nicholas McKay, Satnam Singh
    Debugging Techniques for Dynamically Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:114-122 [Conf]
  9. Satnam Singh
    Death of the RLOC? [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:145-152 [Conf]
  10. Satnam Singh
    Architectural descriptions for FPGA circuits. [Citation Graph (0, 0)][DBLP]
    FCCM, 1995, pp:145-154 [Conf]
  11. Satnam Singh, Carl Johan Lillieroth
    Formal Verification of Reconfigurable Cores. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:25-0 [Conf]
  12. Satnam Singh, Robert Slous
    Accelerating Adobe Photoshop with the Reconfigurable Logic. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:236-244 [Conf]
  13. Anthony Discolo, Tim Harris, Simon Marlow, Simon L. Peyton Jones, Satnam Singh
    Lock Free Data Structures Using STM in Haskell. [Citation Graph (0, 0)][DBLP]
    FLOPS, 2006, pp:65-80 [Conf]
  14. Mary Sheeran, Satnam Singh, Gunnar Stålmarck
    Checking Safety Properties Using Induction and a SAT-Solver. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:108-125 [Conf]
  15. Satnam Singh
    Implementation of a Non-Standard Interpretation System. [Citation Graph (0, 0)][DBLP]
    Functional Programming, 1989, pp:206-224 [Conf]
  16. Satnam Singh
    Using XView/X11 from Miranda. [Citation Graph (0, 0)][DBLP]
    Functional Programming, 1991, pp:352-363 [Conf]
  17. Herman Schmit, Ray Andraka, Philip Friedin, Satnam Singh, Tim Southgate
    The John Henry Syndrome (panel session)(abstract only): humans vs. machines as FPGA designers. [Citation Graph (0, 0)][DBLP]
    FPGA, 2000, pp:101- [Conf]
  18. Satnam Singh
    Integrating FPGAs in high-performance computing: programming models for parallel systems -- the programmer's perspective. [Citation Graph (0, 0)][DBLP]
    FPGA, 2007, pp:133-135 [Conf]
  19. Stefan H.-M. Ludwig, Robert Slous, Satnam Singh
    Implementing Photoshop Filters in Virtex. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:233-242 [Conf]
  20. Donald MacVicar, John W. Patterson, Satnam Singh
    Rendering Postscript Fonts on FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:223-232 [Conf]
  21. Donald MacVicar, Satnam Singh
    Accelerating DTP with Reconfigurable Computing Engines. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:391-395 [Conf]
  22. Nicholas McKay, Satnam Singh
    Dynamic Specialisation of XC6200 FPGAs by Parial Evaluation. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:298-307 [Conf]
  23. Satnam Singh, Philip James-Roxby
    Rapid Construction of Partial Configuration Datastreams from High-Level Constructs Using JBits. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:346-356 [Conf]
  24. Satnam Singh, John W. Patterson, Jim Burns, Michael Dales
    PostscriptTM rendering with virtual hardware. [Citation Graph (0, 0)][DBLP]
    FPL, 1997, pp:428-437 [Conf]
  25. Gérard Berry, Michael Kishinevsky, Satnam Singh
    System Level Design and Verification Using a Synchronous Language. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:433-440 [Conf]
  26. Satnam Singh
    Interface specification for reconfigurable components. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:102-109 [Conf]
  27. Per Bjesse, Koen Claessen, Mary Sheeran, Satnam Singh
    Lava: Hardware Design in Haskell. [Citation Graph (0, 0)][DBLP]
    ICFP, 1998, pp:174-184 [Conf]
  28. Satnam Singh
    Circuit Analysis by Non-Standard Interpretation. [Citation Graph (0, 0)][DBLP]
    Designing Correct Circuits, 1992, pp:119-138 [Conf]
  29. Satnam Singh, Nicholas McKay
    Partial Evaluation of Hardware. [Citation Graph (0, 0)][DBLP]
    Partial Evaluation, 1998, pp:221-230 [Conf]
  30. Satnam Singh, Jefferey Allanach, Haiying Tu, Krishna R. Pattipati, Peter Willett
    Stochastic modeling of a terrorist event via the ASAM system. [Citation Graph (0, 0)][DBLP]
    SMC (6), 2004, pp:5673-5678 [Conf]
  31. Satnam Singh
    Designing Reconfigurable Systems in Lava. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:299-306 [Conf]
  32. Carl Johan Lillieroth, Satnam Singh
    Formal Verification of FPGA Cores. [Citation Graph (0, 0)][DBLP]
    Nord. J. Comput., 1999, v:6, n:3, pp:299-319 [Journal]
  33. Koen Claessen, Mary Sheeran, Satnam Singh
    Using Lava to design and verify recursive and periodic sorters. [Citation Graph (0, 0)][DBLP]
    STTT, 2003, v:4, n:3, pp:349-358 [Journal]
  34. Haiying Tu, Jefferey Allanach, Satnam Singh, Krishna R. Pattipati, Peter Willett
    Information Integration via Hierarchical and Hybrid Bayesian Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Systems, Man, and Cybernetics, Part A, 2006, v:36, n:1, pp:19-33 [Journal]
  35. Tim Harris, Satnam Singh
    Feedback directed implicit parallelism. [Citation Graph (0, 0)][DBLP]
    ICFP, 2007, pp:251-264 [Conf]

  36. A Tutorial on Parallel and Concurrent Programming in Haskell. [Citation Graph (, )][DBLP]


  37. Kiwi: Synthesis of FPGA Circuits from Parallel Programs. [Citation Graph (, )][DBLP]


  38. Finding heap-bounds for hardware synthesis. [Citation Graph (, )][DBLP]


  39. Designing hardware with dynamic memory abstraction. [Citation Graph (, )][DBLP]


  40. Runtime support for multicore Haskell. [Citation Graph (, )][DBLP]


  41. A deterministic multi-way rendezvous library for haskell. [Citation Graph (, )][DBLP]


  42. Declarative data-parallel programming with the accelerator system. [Citation Graph (, )][DBLP]


  43. Rollout strategy for Hidden Markov Model (HMM)-based dynamic sensor scheduling. [Citation Graph (, )][DBLP]


  44. Dynamic fusion of classifiers for fault diagnosis. [Citation Graph (, )][DBLP]


  45. New parallel programming techniques for hardware design. [Citation Graph (, )][DBLP]


  46. Synthesizing FPGA Circuits from Parallel Programs. [Citation Graph (, )][DBLP]


  47. Parallel performance tuning for Haskell. [Citation Graph (, )][DBLP]


  48. Hardware/Software Synthesis and Verification Using Esterel. [Citation Graph (, )][DBLP]


  49. Using C# Attributes to Describe Hardware Artefacts within Kiwi. [Citation Graph (, )][DBLP]


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