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Kevin J. Nowka: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Michael J. Flynn, Kevin J. Nowka, G. Bewick, Eric M. Schwarz, Nhon T. Quach
    The SNAP Project: Towards Sub-Nanosecond Arithmetic. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1995, pp:75-0 [Conf]
  2. Martin S. Schmookler, Kevin J. Nowka
    Leading Zero Anticipation and Detection-A Comparison of Methods. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:7-12 [Conf]
  3. Kevin J. Nowka, H. Peter Hofstee
    Circuits and Microarchitecture for Gigahertz VLSI Designs. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1997, pp:284-287 [Conf]
  4. Ohsang Kwon, Earl E. Swartzlander Jr., Kevin J. Nowka
    A 16-Bit x 16-Bit MAC Design Using Fast 5: 2 Compressors. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:235-0 [Conf]
  5. Juan Antonio Carballo, Kevin J. Nowka, Seung-Moon Yoo, Ivan Vo, Clay Cranford, V. Robert Norman
    Requirement-based design methods for adaptive communications links. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:93-98 [Conf]
  6. Stephen D. Posluszny, N. Aoki, D. Boerstler, P. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, N. Kojima, Ohsang Kwon, K. Lee, D. Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia
    "Timing closure by design, " a high frequency microprocessor design methodology. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:712-717 [Conf]
  7. Ramyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka
    Adaptive Design for Performance-Optimized Robustness. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:3-11 [Conf]
  8. Ohsang Kwon, Earl E. Swartzlander Jr., Kevin J. Nowka
    A fast hybrid carry-lookahead/carry-select adder design. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:149-152 [Conf]
  9. Jente B. Kuang, Hung C. Ngo, Kevin J. Nowka, J. C. Law, Rajiv V. Joshi
    A Low-Overhead Virtual Rail Technique for SRAM Leakage Power Reduction. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:574-584 [Conf]
  10. Kevin J. Nowka, Michael J. Flynn
    System Design Using Wave-Pipelining: A CMOS VLSI Vector Unit. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:2301-2304 [Conf]
  11. Ramyanshu Datta, Jacob A. Abraham, Robert K. Montoye, Wendy Belluomini, Hung Ngo, Chandler McDowell, Jente B. Kuang, Kevin J. Nowka
    A low latency and low power dynamic Carry Save Adder. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:477-480 [Conf]
  12. Hoang Q. Dao, Kevin J. Nowka, Vojin G. Oklobdzija
    Analysis of clocked timing elements for dynamic voltage scaling effects over process parameter variation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:56-59 [Conf]
  13. Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif
    Approaches to run-time and standby mode leakage reduction in global buses. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:188-193 [Conf]
  14. Harmander Deogun, Robert M. Senger, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka
    A dual-VDD boosted pulsed bus technique for low power and low leakage operation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:73-78 [Conf]
  15. Kanak Agarwal, Kevin J. Nowka, Harmander Deogun, Dennis Sylvester
    Power Gating with Multiple Sleep Modes. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:633-637 [Conf]
  16. Harmander Deogun, Rahul M. Rao, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka
    Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:88-93 [Conf]
  17. Praveen Elakkumanan, Jente B. Kuang, Kevin J. Nowka, Ramalingam Sridhar, Rouwaida Kanj, Sani R. Nassif
    SRAM Local Bit Line Access Failure Analyses. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:204-209 [Conf]
  18. Jayakumaran Sivagnaname, Hung C. Ngo, Kevin J. Nowka, Robert K. Montoye, Richard B. Brown
    Controlled-Load Limited Switch Dynamic Logic Circuit. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:83-87 [Conf]
  19. Rahul M. Rao, Kanak Agarwal, Anirudh Devgan, Kevin J. Nowka, Dennis Sylvester, Richard B. Brown
    Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:284-290 [Conf]
  20. Kanak Agarwal, Kevin J. Nowka
    Dynamic Power Management by Combination of Dual Static Supply Voltages. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:85-92 [Conf]
  21. Xiao Yan Yu, Robert K. Montoye, Kevin J. Nowka, Bart R. Zeydel, Vojin G. Oklobdzija
    Circuit Design Style for Energy Efficiency: LSDL and Compound Domino. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:47-55 [Conf]
  22. Alan J. Drake, Kevin J. Nowka, Richard B. Brown
    Evaluation of Dynamic-Threshold Logic for Low-Power VLSI Design in 0.13um PD-SOI. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:263-0 [Conf]
  23. Jayakumaran Sivagnaname, Hung C. Ngo, Kevin J. Nowka, Robert K. Montoye, Richard B. Brown
    Gate-Induced Barrier Field Effect Transistor (GBFET) - A New Thin Film Transistor for Active Matrix Liquid Crystal Display Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:89-93 [Conf]
  24. Ramyanshu Datta, Gary D. Carpenter, Kevin J. Nowka, Jacob A. Abraham
    A Scheme for On-Chip Timing Characterization. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:24-29 [Conf]
  25. David Heidel, Sang H. Dhong, H. Peter Hofstee, Michael Immediato, Kevin J. Nowka, Joel Silberman, Kevin Stawiasz
    High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:234-238 [Conf]
  26. Sachin S. Sapatnekar, Kevin J. Nowka
    Guest Editors' Introduction: New Dimensions in 3D Integration. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:6, pp:496-497 [Journal]
  27. David H. Allen, Sang H. Dhong, H. Peter Hofstee, Jens Leenstra, Kevin J. Nowka, Daniel L. Stasiak, Dieter F. Wendel
    Custom circuit design as a driver of microprocessor performance. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2000, v:44, n:6, pp:799-822 [Journal]
  28. Kevin J. Nowka, Gary D. Carpenter, Bishop Brock
    The design and application of the PowerPC 405LP energy-efficient system-on-a-chip. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2003, v:47, n:5-6, pp:631-640 [Journal]
  29. Harmander Deogun, Dennis Sylvester, Kevin J. Nowka
    Fine grained multi-threshold CMOS for enhanced leakage reduction. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  30. H. Singh, Kanak Agarwal, Dennis Sylvester, Kevin J. Nowka
    Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:11, pp:1215-1224 [Journal]

  31. Technology variability and uncertainty implications for power- efficient VLSI systems. [Citation Graph (, )][DBLP]

  32. Physical design challenges beyond the 22nm node. [Citation Graph (, )][DBLP]

  33. A Design Model for Random Process Variability. [Citation Graph (, )][DBLP]

  34. Statistical yield analysis of silicon-on-insulator embedded DRAM. [Citation Graph (, )][DBLP]

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