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Conferences in DBLP

High Performance Embedded Architectures and Compilers (hipeac)
2005 (conf/hipeac/2005)

  1. Markus Levy
    Using EEMBC Benchmarks to Understand Processor Behavior in Embedded Applications. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2005, pp:3-4 [Conf]
  2. Per Stenström
    The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2005, pp:5- [Conf]
  3. Hyunseok Lee, Yuan Lin, Yoav Harel, Mark Woh, Scott A. Mahlke, Trevor N. Mudge, Krisztián Flautner
    Software Defined Radio - A High Performance Embedded Challenge. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2005, pp:6-26 [Conf]
  4. Grigori Fursin, Albert Cohen, Michael F. P. O'Boyle, Olivier Temam
    A Practical Method for Quickly Evaluating Program Optimizations. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2005, pp:29-46 [Conf]
  5. Michael Van Biesbrouck, Lieven Eeckhout, Brad Calder
    Efficient Sampling Startup for Sampled Processor Simulation. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2005, pp:47-67 [Conf]
  6. Jia Yu, Jun Yang, Shaojie Chen, Yan Luo, Laxmi N. Bhuyan
    Enhancing Network Processor Simulation Speed with Statistical Input Sampling. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2005, pp:68-83 [Conf]
  7. Ke Ning, David R. Kaeli
    Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2005, pp:87-101 [Conf]
  8. Michael J. Geiger, Sally A. McKee, Gary S. Tyson
    Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2005, pp:102-115 [Conf]
  9. David Moloney, Dermot Geraghty, Colm McSweeney, Ciarán McElroy
    Streaming Sparse Matrix Compression/Decompression. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2005, pp:116-129 [Conf]
  10. Gansha Wu, Xin Zhou, Guei-Yuan Lueh, Jesse Z. Fang, Peng Guo, Jinzhan Peng, Victor Ying
    XAMM: A High-Performance Automatic Memory Management System with Memory-Constrained Designs. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2005, pp:130-149 [Conf]
  11. Weidong Shi, Chenghuai Lu, Hsien-Hsin S. Lee
    Memory-Centric Security Architecture. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2005, pp:153-168 [Conf]
  12. Abdulhadi Shoufan, Sorin A. Huss, Murtuza Cutleriwala
    A Novel Batch Rekeying Processor Architecture for Secure Multicast Key Management. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2005, pp:169-183 [Conf]
  13. Mahadevan Gomathisankaran, Akhilesh Tyagi
    Arc3D: A 3D Obfuscation Architecture. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2005, pp:184-199 [Conf]
  14. Jinpyo Kim, Sreekumar V. Kodakara, Wei-Chung Hsu, David J. Lilja, Pen-Chung Yew
    Dynamic Code Region (DCR) Based Program Phase Tracking and Prediction for Dynamic Optimizations. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2005, pp:203-217 [Conf]
  15. Sebastian Pop, Albert Cohen, Georges-André Silber
    Induction Variable Analysis with Delayed Abstractions. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2005, pp:218-232 [Conf]
  16. Dries Buytaert, Kris Venstermans, Lieven Eeckhout, Koen De Bosschere
    Garbage Collection Hints. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2005, pp:233-248 [Conf]
  17. Bengu Li, Ganesh Venkatesh, Brad Calder, Rajiv Gupta
    Exploiting a Computation Reuse Cache to Reduce Energy in Network Processors. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2005, pp:251-265 [Conf]
  18. Pedro Javier García, Jose Flich, José Duato, Ian Johnson, Francisco J. Quiles, Finbar Naven
    Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2005, pp:266-285 [Conf]
  19. Victor Moya Del Barrio, Carlos González, Jordi Roca, Agustin Fernández, Roger Espasa
    A Single (Unified) Shader GPU Microarchitecture for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2005, pp:286-301 [Conf]
  20. Hyun-Gyu Kim, Hyeong-Cheol Oh
    A Low-Power DSP-Enhanced 32-Bit EISC Processor. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2005, pp:302-316 [Conf]
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