Conferences in DBLP
Markus Levy Using EEMBC Benchmarks to Understand Processor Behavior in Embedded Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Per Stenström The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges. [Citation Graph (0, 0)][DBLP ] Conf ] Hyunseok Lee , Yuan Lin , Yoav Harel , Mark Woh , Scott A. Mahlke , Trevor N. Mudge , Krisztián Flautner Software Defined Radio - A High Performance Embedded Challenge. [Citation Graph (0, 0)][DBLP ] Conf ] Grigori Fursin , Albert Cohen , Michael F. P. O'Boyle , Olivier Temam A Practical Method for Quickly Evaluating Program Optimizations. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Van Biesbrouck , Lieven Eeckhout , Brad Calder Efficient Sampling Startup for Sampled Processor Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Jia Yu , Jun Yang , Shaojie Chen , Yan Luo , Laxmi N. Bhuyan Enhancing Network Processor Simulation Speed with Statistical Input Sampling. [Citation Graph (0, 0)][DBLP ] Conf ] Ke Ning , David R. Kaeli Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Michael J. Geiger , Sally A. McKee , Gary S. Tyson Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation. [Citation Graph (0, 0)][DBLP ] Conf ] David Moloney , Dermot Geraghty , Colm McSweeney , Ciarán McElroy Streaming Sparse Matrix Compression/Decompression. [Citation Graph (0, 0)][DBLP ] Conf ] Gansha Wu , Xin Zhou , Guei-Yuan Lueh , Jesse Z. Fang , Peng Guo , Jinzhan Peng , Victor Ying XAMM: A High-Performance Automatic Memory Management System with Memory-Constrained Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Weidong Shi , Chenghuai Lu , Hsien-Hsin S. Lee Memory-Centric Security Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Abdulhadi Shoufan , Sorin A. Huss , Murtuza Cutleriwala A Novel Batch Rekeying Processor Architecture for Secure Multicast Key Management. [Citation Graph (0, 0)][DBLP ] Conf ] Mahadevan Gomathisankaran , Akhilesh Tyagi Arc3D: A 3D Obfuscation Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Jinpyo Kim , Sreekumar V. Kodakara , Wei-Chung Hsu , David J. Lilja , Pen-Chung Yew Dynamic Code Region (DCR) Based Program Phase Tracking and Prediction for Dynamic Optimizations. [Citation Graph (0, 0)][DBLP ] Conf ] Sebastian Pop , Albert Cohen , Georges-André Silber Induction Variable Analysis with Delayed Abstractions. [Citation Graph (0, 0)][DBLP ] Conf ] Dries Buytaert , Kris Venstermans , Lieven Eeckhout , Koen De Bosschere Garbage Collection Hints. [Citation Graph (0, 0)][DBLP ] Conf ] Bengu Li , Ganesh Venkatesh , Brad Calder , Rajiv Gupta Exploiting a Computation Reuse Cache to Reduce Energy in Network Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Pedro Javier García , Jose Flich , José Duato , Ian Johnson , Francisco J. Quiles , Finbar Naven Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Victor Moya Del Barrio , Carlos González , Jordi Roca , Agustin Fernández , Roger Espasa A Single (Unified) Shader GPU Microarchitecture for Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Hyun-Gyu Kim , Hyeong-Cheol Oh A Low-Power DSP-Enhanced 32-Bit EISC Processor. [Citation Graph (0, 0)][DBLP ] Conf ] 