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Krisztián Flautner :
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Krisztián Flautner , Richard Uhlig , Steven K. Reinhardt , Trevor N. Mudge Thread Level Parallelism and Interactive Performance of Desktop Applications. [Citation Graph (0, 0)][DBLP ] ASPLOS, 2000, pp:129-138 [Conf ] Taeho Kgil , Shaun D'Souza , Ali G. Saidi , Nathan L. Binkert , Ronald G. Dreslinski , Trevor N. Mudge , Steven K. Reinhardt , Krisztián Flautner PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor. [Citation Graph (0, 0)][DBLP ] ASPLOS, 2006, pp:117-128 [Conf ] Sami Yehia , Nathan Clark , Scott A. Mahlke , Krisztián Flautner Exploring the design space of LUT-based transparent accelerators. [Citation Graph (0, 0)][DBLP ] CASES, 2005, pp:11-21 [Conf ] Krisztián Flautner Cutting across layers of abstraction: : removing obstacles from the advancement of embedded systems. [Citation Graph (0, 0)][DBLP ] CODES+ISSS, 2006, pp:265- [Conf ] Bo Zhai , David Blaauw , Dennis Sylvester , Krisztián Flautner Theoretical and practical limits of dynamic voltage scaling. [Citation Graph (0, 0)][DBLP ] DAC, 2004, pp:868-873 [Conf ] Krisztián Flautner , David Flynn , David Roberts , Dipesh I. Patel IEM926: An Energy Efficient SoC with Dynamic Voltage Scaling. [Citation Graph (0, 0)][DBLP ] DATE, 2004, pp:324-329 [Conf ] Jürgen Teich , Stefanos Kaxiras , Toomas P. Plaks , Krisztián Flautner Topic 18: Embedded Parallel Systems. [Citation Graph (0, 0)][DBLP ] Euro-Par, 2006, pp:1179- [Conf ] Hyunseok Lee , Yuan Lin , Yoav Harel , Mark Woh , Scott A. Mahlke , Trevor N. Mudge , Krisztián Flautner Software Defined Radio - A High Performance Embedded Challenge. [Citation Graph (0, 0)][DBLP ] HiPEAC, 2005, pp:6-26 [Conf ] Steven M. Martin , Krisztián Flautner , Trevor N. Mudge , David Blaauw Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads. [Citation Graph (0, 0)][DBLP ] ICCAD, 2002, pp:721-725 [Conf ] Nathan Clark , Jason A. Blome , Michael L. Chu , Scott A. Mahlke , Stuart Biles , Krisztián Flautner An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors. [Citation Graph (0, 0)][DBLP ] ISCA, 2005, pp:272-283 [Conf ] Krisztián Flautner , Nam Sung Kim , Steve Martin , David Blaauw , Trevor N. Mudge Drowsy Caches: Simple Techniques for Reducing Leakage Power. [Citation Graph (0, 0)][DBLP ] ISCA, 2002, pp:148-157 [Conf ] Yuan Lin , Hyunseok Lee , Mark Woh , Yoav Harel , Scott A. Mahlke , Trevor N. Mudge , Chaitali Chakrabarti , Krisztián Flautner SODA: A Low-power Architecture For Software Radio. [Citation Graph (0, 0)][DBLP ] ISCA, 2006, pp:89-101 [Conf ] David Roberts , Todd M. Austin , David Blaauw , Trevor N. Mudge , Krisztián Flautner Error Analysis for the Support of Robust Voltage Scaling. [Citation Graph (0, 0)][DBLP ] ISQED, 2005, pp:65-70 [Conf ] Nathan Clark , Manjunath Kudlur , Hyunchul Park , Scott A. Mahlke , Krisztián Flautner Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization. [Citation Graph (0, 0)][DBLP ] MICRO, 2004, pp:30-40 [Conf ] Dan Ernst , Nam Sung Kim , Shidhartha Das , Sanjay Pant , Rajeev R. Rao , Toan Pham , Conrad H. Ziesler , David Blaauw , Todd M. Austin , Krisztián Flautner , Trevor N. Mudge Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. [Citation Graph (0, 0)][DBLP ] MICRO, 2003, pp:7-18 [Conf ] Nam Sung Kim , Krisztián Flautner , David Blaauw , Trevor N. Mudge Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction. [Citation Graph (0, 0)][DBLP ] MICRO, 2002, pp:219-230 [Conf ] Krisztián Flautner , Steven K. Reinhardt , Trevor N. Mudge Automatic performance setting for dynamic voltage scaling. [Citation Graph (0, 0)][DBLP ] MOBICOM, 2001, pp:260-271 [Conf ] Krisztián Flautner , Trevor N. Mudge Vertigo: Automatic Performance-Setting for Linux. [Citation Graph (0, 0)][DBLP ] OSDI, 2002, pp:- [Conf ] Todd M. Austin , David Blaauw , Trevor N. Mudge , Krisztián Flautner Making Typical Silicon Matter with Razor. [Citation Graph (0, 0)][DBLP ] IEEE Computer, 2004, v:37, n:3, pp:57-65 [Journal ] Nam Sung Kim , Todd M. Austin , David Blaauw , Trevor N. Mudge , Krisztián Flautner , Jie S. Hu , Mary Jane Irwin , Mahmut T. Kandemir , Narayanan Vijaykrishnan Leakage Current: Moore's Law Meets Static Power. [Citation Graph (0, 0)][DBLP ] IEEE Computer, 2003, v:36, n:12, pp:68-75 [Journal ] David Blaauw , Steve Martin , Trevor N. Mudge , Krisztián Flautner Leakage Current Reduction in VLSI Systems. [Citation Graph (0, 0)][DBLP ] Journal of Circuits, Systems, and Computers, 2002, v:11, n:6, pp:621-636 [Journal ] Dan Ernst , Shidhartha Das , Seokwoo Lee , David Blaauw , Todd M. Austin , Trevor N. Mudge , Nam Sung Kim , Krisztián Flautner Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation. [Citation Graph (0, 0)][DBLP ] IEEE Micro, 2004, v:24, n:6, pp:10-20 [Journal ] Nam Sung Kim , Krisztián Flautner , David Blaauw , Trevor N. Mudge Circuit and microarchitectural techniques for reducing cache leakage power. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2004, v:12, n:2, pp:167-184 [Journal ] Bo Zhai , David T. Blaauw , Dennis Sylvester , Krisztián Flautner The limit of dynamic voltage scaling and insomniac dynamic voltage scaling. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1239-1252 [Journal ] Krisztián Flautner Architectural Trade-Offs for Fault Tolerant Multi-Core Systems. [Citation Graph (0, 0)][DBLP ] IOLTS, 2007, pp:261- [Conf ] Krisztián Flautner Blurring the Layers of Abstractions: Time to Take a Step Back? [Citation Graph (0, 0)][DBLP ] IOLTS, 2007, pp:127- [Conf ] Mark Woh , Sangwon Seo , Hyunseok Lee , Yuan Lin , Scott A. Mahlke , Trevor N. Mudge , Chaitali Chakrabarti , Krisztián Flautner The Next Generation Challenge for Software Defined Radio. [Citation Graph (0, 0)][DBLP ] SAMOS, 2007, pp:343-354 [Conf ] Yuan Lin , Hyunseok Lee , Mark Woh , Yoav Harel , Scott A. Mahlke , Trevor N. Mudge , Chaitali Chakrabarti , Krisztián Flautner SODA: A High-Performance DSP Architecture for Software-Defined Radio. [Citation Graph (0, 0)][DBLP ] IEEE Micro, 2007, v:27, n:1, pp:114-123 [Journal ] Life on the Treadmill. [Citation Graph (, )][DBLP ] SoC-C: efficient programming abstractions for heterogeneous multicore systems on chip. [Citation Graph (, )][DBLP ] Addressing design margins through error-tolerant circuits. [Citation Graph (, )][DBLP ] Optimize your power and performance yields and regain those sleepless nights. [Citation Graph (, )][DBLP ] The Wall Ahead is Made of Rubber. [Citation Graph (, )][DBLP ] Liquid SIMD: Abstracting SIMD Hardware using Lightweight Dynamic Mapping. [Citation Graph (, )][DBLP ] AnySP: anytime anywhere anyway signal processing. [Citation Graph (, )][DBLP ] Evolution of thread-level parallelism in desktop applications. [Citation Graph (, )][DBLP ] From SODA to scotch: The evolution of a wireless baseband processor. [Citation Graph (, )][DBLP ] Reconfigurable energy efficient near threshold cache architectures. [Citation Graph (, )][DBLP ] Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor. [Citation Graph (, )][DBLP ] Design and Implementation of Turbo Decoders for Software Defined Radio. [Citation Graph (, )][DBLP ] The State of ESL Design [Roundtable]. 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