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Roger Espasa: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Manel Fernández, Roger Espasa
    Link-Time Optimization Techniques for Eliminating Conditional Branch Redundancies. [Citation Graph (0, 0)][DBLP]
    Interaction between Compilers and Computer Architectures, 2004, pp:87-96 [Conf]
  2. Jesús Corbal, Roger Espasa, Mateo Valero
    On the Efficiency of Reductions in µ-SIMD Media Extensions. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:83-0 [Conf]
  3. Manel Fernández, Roger Espasa
    Speculative Alias Analysis for Executable Code. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2002, pp:222-231 [Conf]
  4. Jesús Corbal, Roger Espasa, Mateo Valero
    Command Vector Memory Systems: High Performance at Low Cost. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1998, pp:68-0 [Conf]
  5. Luis Villa, Roger Espasa, Mateo Valero
    Effective Usage of Vector Registers in Advanced Vector Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1997, pp:250-260 [Conf]
  6. Eduard Ayguadé, Fredrik Dahlgren, Christine Eisenbeis, Roger Espasa, Guang R. Gao, Henk L. Muller, Rizos Sakellariou, André Seznec
    Topic 08+13: Instruction-Level Parallelism and Computer Architecture. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2001, pp:385- [Conf]
  7. Manel Fernández, Roger Espasa, Saumya K. Debray
    Load Redundancy Elimination on Executable Code. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2001, pp:221-229 [Conf]
  8. Victor Moya Del Barrio, Carlos González, Jordi Roca, Agustin Fernández, Roger Espasa
    A Single (Unified) Shader GPU Microarchitecture for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2005, pp:286-301 [Conf]
  9. Roger Espasa, Mateo Valero
    Decoupled Vector Architectures. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:281-290 [Conf]
  10. Roger Espasa, Mateo Valero
    Multithreaded Vector Architectures. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:237-0 [Conf]
  11. Manel Fernández, Roger Espasa
    Link-Time Path-Sensitive Memory Redundancy Elimination. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:300-310 [Conf]
  12. Jesús Corbal, Roger Espasa, Mateo Valero
    DLP + TLP Processors for the Next Generation of Media Workloads. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:219-228 [Conf]
  13. Roger Espasa, Mateo Valero
    A Victim Cache for Vector Registers. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1997, pp:293-300 [Conf]
  14. Roger Espasa, Mateo Valero, James E. Smith
    Vector Architectures: Past, Present and Future. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1998, pp:425-432 [Conf]
  15. Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero
    Adding a vector unit to a superscalar processor. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:1-10 [Conf]
  16. Luis Villa, Roger Espasa, Mateo Valero
    A Performance Study of Out-of-order Vector Architectures and Short Registers. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1998, pp:37-44 [Conf]
  17. Roger Espasa, Federico Ardanaz, Julio Gago, Roger Gramunt, Isaac Hernandez, Toni Juan, Joel S. Emer, Stephen Felix, P. Geoffrey Lowney, Matthew Mattina, André Seznec
    Tarantula: A Vector Extension to the Alpha Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:281-0 [Conf]
  18. Jesús Corbal, Roger Espasa, Mateo Valero
    Three-dimensional memory vectorization for high bandwidth media memory systems. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:149-160 [Conf]
  19. Jesús Corbal, Roger Espasa, Mateo Valero
    Exploiting a New Level of DLP in Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    MICRO, 1999, pp:72-0 [Conf]
  20. Roger Espasa, Mateo Valero, James E. Smith
    Out-of-Order Vector Architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 1997, pp:160-170 [Conf]
  21. Alexandre Farcy, Olivier Temam, Roger Espasa, Toni Juan
    Dataflow Analysis of Branch Mispredictions and Its Application to Early Resolution of Branch Outcomes. [Citation Graph (0, 0)][DBLP]
    MICRO, 1998, pp:59-68 [Conf]
  22. Victor Moya Del Barrio, Carlos González, Jordi Roca, Agustin Fernández, Roger Espasa
    Shader Performance Analysis on a Modern GPU Architecture. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:355-364 [Conf]
  23. Roger Espasa, Mateo Valero, David A. Padua, Marta Jiménez, Eduard Ayguadé
    Quantitative analysis of vector code. [Citation Graph (0, 0)][DBLP]
    PDP, 1995, pp:452-463 [Conf]
  24. Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero
    A cost effective architecture for vectorizable numerical and multimedia applications. [Citation Graph (0, 0)][DBLP]
    SPAA, 2001, pp:103-112 [Conf]
  25. Francisca Quintana, Roger Espasa, Mateo Valero
    An ISA Comparison Between Superscalar and Vector Processors. [Citation Graph (0, 0)][DBLP]
    VECPAR, 1998, pp:548-560 [Conf]
  26. Luis Villa, Roger Espasa, Mateo Valero
    Registers Size Influence on Vector Architectures. [Citation Graph (0, 0)][DBLP]
    VECPAR, 1998, pp:439-451 [Conf]
  27. Joel S. Emer, Pritpal Ahuja, Eric Borch, Artur Klauser, Chi-Keung Luk, Srilatha Manne, Shubhendu S. Mukherjee, Harish Patil, Steven Wallace, Nathan L. Binkert, Roger Espasa, Toni Juan
    Asim: A Performance Model Framework. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2002, v:35, n:2, pp:68-76 [Journal]
  28. Manel Fernández, Roger Espasa, Saumya K. Debray
    Load redundancy elimination on executable code. [Citation Graph (0, 0)][DBLP]
    Concurrency and Computation: Practice and Experience, 2003, v:15, n:10, pp:979-997 [Journal]
  29. Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero
    A Cost-Effective Architecture for Vectorizable Numerical and Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    Theory Comput. Syst., 2003, v:36, n:5, pp:575-593 [Journal]
  30. André Seznec, Roger Espasa
    Conflict-Free Accesses to Strided Vectors on a Banked Cache. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:7, pp:913-196 [Journal]
  31. Roger Espasa, Mateo Valero
    A Simulation Study of Decoupled Vector Architectures. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 1999, v:14, n:2, pp:124-152 [Journal]
  32. Jordi Roca, Victor Moya Del Barrio, Carlos González, Chema Solis, Agustin Fernández, Roger Espasa
    Workload Characterization of 3D Games. [Citation Graph (0, 0)][DBLP]
    IISWC, 2006, pp:17-26 [Conf]

  33. Larrabee: A Many-Core Intel Architecture for Visual Computing. [Citation Graph (, )][DBLP]


  34. ATTILA: a cycle-level execution-driven simulator for modern GPU architectures. [Citation Graph (, )][DBLP]


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