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Per Stenström: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Per Stenström, Erik Hagersten, David J. Lilja, Margaret Martonosi, Madan Venugopal
    Trends in Shared Memory Multiprocessing. [Citation Graph (1, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:12, pp:44-50 [Journal]
  2. Fredrik Warg, Per Stenström
    Limits on Speculative Module-Level Parallelism in Imperative and Object-Oriented Programs on CMP Platforms. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:221-230 [Conf]
  3. Haakon Dybdahl, Per Stenström
    Enhancing Last-Level Cache Performance by Block Bypassing and Early Miss Determination. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:52-66 [Conf]
  4. Jonas Skeppstedt, Per Stenström
    Simple Compiler Algorithms to Reduce Ownership Operhead in Cache Coherence Protocols. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1994, pp:286-296 [Conf]
  5. Martin Kämpe, Per Stenström, Michel Dubois
    Self-correcting LRU replacement policies. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:181-191 [Conf]
  6. Jaeheon Jeong, Per Stenström, Michel Dubois
    Simple penalty-sensitive replacement policies for caches. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2006, pp:341-352 [Conf]
  7. Martin Thuresson, Per Stenström
    Evaluation of extended dictionary-based static code compression schemes. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2005, pp:77-86 [Conf]
  8. Fredrik Warg, Per Stenström
    Reducing misspeculation overhead for module-level speculative execution. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2005, pp:289-298 [Conf]
  9. Jochen Hollmann, Anders Ardö, Per Stenström
    An Evaluation of Document Prefetching in a Distributed Digital Library. [Citation Graph (0, 0)][DBLP]
    ECDL, 2003, pp:276-287 [Conf]
  10. Ulf Assarsson, Per Stenström
    A Case Study of Load Distribution in Parallel View Frustum Culling and Collision Detection. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2001, pp:663-673 [Conf]
  11. Silvia M. Müller, Per Stenström, Mateo Valero, Stamatis Vassiliadis
    Parallel Computer Architecture. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2000, pp:537-538 [Conf]
  12. Per Stenström, Jonas Skeppstedt
    A Performance Tuning Approach for Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1997, pp:72-83 [Conf]
  13. Mårten Björkman, Fredrik Dahlgren, Per Stenström
    Using hints to reduce the read miss penalty for flat COMA protocols. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1995, pp:242-251 [Conf]
  14. Per Stenström
    Introduction. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:520-521 [Conf]
  15. Per Stenström
    One Chip, One Server: How Do We Exploit Its Power? [Citation Graph (0, 0)][DBLP]
    HiPC, 2003, pp:405- [Conf]
  16. Haakon Dybdahl, Per Stenström, Lasse Natvig
    A Cache-Partitioning Aware Replacement Policy for Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HiPC, 2006, pp:22-34 [Conf]
  17. Per Stenström
    The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2005, pp:5- [Conf]
  18. Fredrik Dahlgren, Per Stenström
    Effectiveness of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:68-77 [Conf]
  19. Martin Kämpe, Per Stenström, Michel Dubois
    The FAB Predictor: Using Fourier Analysis to Predict the Outcome of Conditional Branches. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:223-232 [Conf]
  20. Magnus Karlsson, Fredrik Dahlgren, Per Stenström
    A Prefetching Technique for Irregular Accesses to Linked Data Structures. [Citation Graph (0, 0)][DBLP]
    HPCA, 2000, pp:206-217 [Conf]
  21. Magnus Karlsson, Per Stenström
    Performance Evaluation of a Cluster-Based Multiprocessor Built from ATM Switches and Bus-Based Multiprocessor Servers. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:4-13 [Conf]
  22. Fredrik Dahlgren, Michel Dubois, Per Stenström
    Fixed and Adaptive Sequential Prefetching in Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:56-63 [Conf]
  23. Fredrik Dahlgren, Per Stenström
    Reducing the Write Traffic for a Hybrid Cache Protocol. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1994, pp:166-173 [Conf]
  24. Magnus Ekman, Per Stenström
    Performance and Power Impact of Issue-width in Chip-Multiprocessor Cores. [Citation Graph (0, 0)][DBLP]
    ICPP, 2003, pp:359-368 [Conf]
  25. Jonas Jalminger, Per Stenström
    A Novel Approach to Cache Block Reuse Predictions. [Citation Graph (0, 0)][DBLP]
    ICPP, 2003, pp:294-0 [Conf]
  26. Fong Pong, Per Stenström, Michel Dubois
    An Integrated Methodology for the Verification of Directory-Based Cache Protocols. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1994, pp:158-165 [Conf]
  27. Per Stenström, Fredrik Dahlgren, Lars Lundberg
    A Lockup-Free Multiprocessor Cache Design. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1991, pp:246-250 [Conf]
  28. Magnus Ekman, Per Stenström
    A Cost-Effective Main Memory Organization for Future Servers. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  29. Håkan Grahn, Per Stenström
    Relative Performance of Hardware and Software-Only Directory Protocols Under Latency Tolerating and Reducing Techniques. [Citation Graph (0, 0)][DBLP]
    IPPS, 1997, pp:500-0 [Conf]
  30. Jochen Hollmann, Anders Ardö, Per Stenström
    Empirical Observations Regarding Predictability in User Access-Behavior in a Distributed Digital Library System. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  31. Jim Nilsson, Anders Landin, Per Stenström
    The Coherence Predictor Cache: A Resource-Efficient and Accurate Coherence Prediction Infrastructure. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:10- [Conf]
  32. Peter Rundberg, Per Stenström
    Speculative Lock Reordering: Optimistic Out-of-Order Execution of Critical Sections. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:11- [Conf]
  33. Per Stenström
    A Latency-Hiding Scheme for Multiprocessors with Buffered Multistage Networks. [Citation Graph (0, 0)][DBLP]
    IPPS, 1992, pp:39-42 [Conf]
  34. Fredrik Warg, Per Stenström
    Improving Speculative Thread-Level Parallelism Through Module Run-Length Prediction. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:12- [Conf]
  35. Fredrik Dahlgren, Michel Dubois, Per Stenström
    Combined Performance Gains of Simple Cache Protocol Extensions. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:187-197 [Conf]
  36. Michel Dubois, Jonas Skeppstedt, Livio Ricciulli, Krishnan Ramamurthy, Per Stenström
    The Detection and Elimination of Useless Misses in Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:88-97 [Conf]
  37. Håkan Grahn, Per Stenström
    Efficient Strategies for Software-Only Protocols in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1995, pp:38-47 [Conf]
  38. Magnus Ekman, Per Stenström
    A Robust Main-Memory Compression Scheme. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:74-85 [Conf]
  39. Ashley Saulsbury, Fredrik Dahlgren, Per Stenström
    Recency-based TLB preloading. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:117-127 [Conf]
  40. Per Stenström
    A Cache Consistency Protocol for Multiprocessors with Multistage Networks. [Citation Graph (0, 0)][DBLP]
    ISCA, 1989, pp:407-415 [Conf]
  41. Per Stenström, Mats Brorsson, Lars Sandberg
    An Adaptive Cache Coherence Protocol Optimized for Migratory Sharing. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:109-118 [Conf]
  42. Per Stenström, Truman Joe, Anoop Gupta
    Comparative Performance Evaluation of Cache-Coherent NUMA and COMA Architectures. [Citation Graph (0, 0)][DBLP]
    ISCA, 1992, pp:80-91 [Conf]
  43. Magnus Ekman, Per Stenström, Fredrik Dahlgren
    TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:243-246 [Conf]
  44. Jianwei Chen, Michel Dubois, Per Stenström
    Integrating complete-system and user-level performance/power simulators: the SimWattch approach. [Citation Graph (0, 0)][DBLP]
    ISPASS, 2003, pp:1-10 [Conf]
  45. Thomas Lundqvist, Per Stenström
    Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques. [Citation Graph (0, 0)][DBLP]
    LCTES, 1998, pp:1-15 [Conf]
  46. Fredrik Dahlgren, Per Stenström
    On Reconfigurable On-Chip Data Caches. [Citation Graph (0, 0)][DBLP]
    MICRO, 1991, pp:189-198 [Conf]
  47. Håkan Nilsson, Per Stenström
    An Adaptive Update-Based Cache Coherence Protocol for Reduction of Miss Rate and Traffic. [Citation Graph (0, 0)][DBLP]
    PARLE, 1994, pp:363-374 [Conf]
  48. Per Stenström, Lars Philipson
    A Layered Emulator for Design Evaluation of MIMD Multiprocessors with Shared Memory. [Citation Graph (0, 0)][DBLP]
    PARLE (1), 1987, pp:329-344 [Conf]
  49. Thomas Lundqvist, Per Stenström
    A Method to Improve the Estimated Worst-Case Performance of Data Caching. [Citation Graph (0, 0)][DBLP]
    RTCSA, 1999, pp:255-262 [Conf]
  50. Thomas Lundqvist, Per Stenström
    Timing Anomalies in Dynamically Scheduled Microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1999, pp:12-21 [Conf]
  51. Magnus Karlsson, Per Stenström
    An analytical model of the working-set sizes in decision-support systems. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 2000, pp:275-285 [Conf]
  52. Håkan Nilsson, Per Stenström
    The Scalable Tree Protocol - A Cache Coherence Approach for Large-Scale Multiprocessors. [Citation Graph (0, 0)][DBLP]
    SPDP, 1992, pp:498-506 [Conf]
  53. Magnus Ekman, Per Stenström
    A case for multi-level main memory. [Citation Graph (0, 0)][DBLP]
    WMPI, 2004, pp:1-8 [Conf]
  54. Per Stenström, Erik Hagersten, David J. Lilja, Margaret Martonosi, Madan Venugopal
    Shared-memory multiprocessing: Current state and future directions. [Citation Graph (0, 0)][DBLP]
    Advances in Computers, 2000, v:53, n:, pp:2-55 [Journal]
  55. Fredrik Dahlgren, Per Stenström, Mårten Björkman
    Reducing the Read-Miss Penalty for Flat COMA Protocols. [Citation Graph (0, 0)][DBLP]
    Comput. J., 1997, v:40, n:4, pp:208-219 [Journal]
  56. Per Stenström
    Reducing Contention in Sharde-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1988, v:21, n:11, pp:26-37 [Journal]
  57. Per Stenström
    A Survey of Cache Coherence Schemes for Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1990, v:23, n:6, pp:12-24 [Journal]
  58. Per Stenström, Mats Brorsson, Fredrik Dahlgren, Håkan Grahn, Michel Dubois
    Boosting the Performance of Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:7, pp:63-70 [Journal]
  59. Per Stenström, Fredrik Dahlgren
    Applications for Shared Memory Multiprocessors (Guest Editors' Introduction). [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1996, v:29, n:12, pp:29-31 [Journal]
  60. Peter Rundberg, Per Stenström
    An All-Software Thread-Level Data Dependence Speculation System for Multiprocessors. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2001, v:3, n:, pp:- [Journal]
  61. Fredrik Dahlgren, Per Stenström
    Using Write Caches to Improve Performance of Cache Coherence Protocols in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1995, v:26, n:2, pp:193-210 [Journal]
  62. Michel Dubois, Jonas Skeppstedt, Per Stenström
    Essential Misses and Data Traffic in Coherence Protocols. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1995, v:29, n:2, pp:108-125 [Journal]
  63. Håkan Grahn, Per Stenström
    Comparative Evaluation of Latency-Tolerating and -Reducing Techniques for Hardware-Only and Software-Only Directory Protocols. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2000, v:60, n:7, pp:807-834 [Journal]
  64. Håkan Grahn, Per Stenström
    Evaluation of a Competitive-Update Cache Coherence Protocol with Migratory Data Detection. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1996, v:39, n:2, pp:168-180 [Journal]
  65. Magnus Karlsson, Per Stenström
    Effectivness of Dynamic Prefetching in Multiple-Writer Distributed Virtual Shared-Memory Systems. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1997, v:43, n:2, pp:79-93 [Journal]
  66. Jonas Skeppstedt, Fredrik Dahlgren, Per Stenström
    Evaluation of Compiler-Controlled Updating to Reduce Coherence-Miss Penalties in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1999, v:56, n:2, pp:122-143 [Journal]
  67. Burkhard Monien, Guang Gao, Horst Simon, Paul G. Spirakis, Per Stenström
    Introduction. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2006, v:66, n:5, pp:615-616 [Journal]
  68. Håkan Grahn, Per Stenström
    A comparative evaluation of hardware-only and software-only directory protocols in shared-memory multiprocessors. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2004, v:50, n:9, pp:537-561 [Journal]
  69. Mats Brorsson, Per Stenström
    Characterising and Modelling Shared Memory Accesses in Multiprocessor Programs. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1996, v:22, n:6, pp:869-893 [Journal]
  70. Thomas Lundqvist, Per Stenström
    An Integrated Path and Timing Analysis Method based on Cycle-Level Symbolic Execution. [Citation Graph (0, 0)][DBLP]
    Real-Time Systems, 1999, v:17, n:2-3, pp:183-207 [Journal]
  71. Fredrik Dahlgren, Michel Dubois, Per Stenström
    Performance Evaluation and Cost Analysis of Cache Protocol Extensions for Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:10, pp:1041-1055 [Journal]
  72. Frank Mueller, Per Stenström
    Introduction to the special issue. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2005, v:4, n:1, pp:1-2 [Journal]
  73. Jonas Skeppstedt, Per Stenström
    Using Dataflow Analysis Techniques to Reduce Ownership Overhead in Cache Coherence Protocols. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 1996, v:18, n:6, pp:659-682 [Journal]
  74. Fredrik Dahlgren, Michel Dubois, Per Stenström
    Sequential Hardware Prefetching in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1995, v:6, n:7, pp:733-746 [Journal]
  75. Fredrik Dahlgren, Per Stenström
    Evaluation of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1996, v:7, n:4, pp:385-398 [Journal]
  76. Jonas Jalminger, Per Stenström
    A cache block reuse prediction scheme. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:7, pp:373-385 [Journal]
  77. Jonas Jalminger, Per Stenström
    Improvement of energy-efficiency in off-chip caches by selective prefetching. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2002, v:26, n:3, pp:107-121 [Journal]
  78. Marco Galluzzi, Enrique Vallejo, Adrián Cristal, Fernando Vallejo, Ramón Beivide, Per Stenström, James E. Smith, Mateo Valero
    Implicit Transactional Memory in Kilo-Instruction Multiprocessors. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2007, pp:339-353 [Conf]
  79. Shekhar Borkar, Norman P. Jouppi, Per Stenström
    Microprocessors in the era of terascale integration. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:237-242 [Conf]
  80. Mridha Mohammad Waliullah, Per Stenström
    Starvation-Free Transactional Memory-System Protocols. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2007, pp:280-291 [Conf]
  81. Mafijul Md. Islam, Alexander Busck, Mikael Engbom, Simji Lee, Michel Dubois, Per Stenström
    Loop-level Speculative Parallelism in Embedded Applications. [Citation Graph (0, 0)][DBLP]
    ICPP, 2007, pp:3- [Conf]
  82. Per Stenström
    IPDPS Panel: Is the Multi-Core Roadmap going to Live Up to its Promises? [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:14- [Conf]
  83. Mafijul Islam, Per Stenström
    Reduction of Energy Consumption in Processors by Early Detection and Bypassing of Trivial Operations. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:28-34 [Conf]
  84. Martin Thuresson, Magnus Själander, Magnus Bjork, Lars Svensson, Per Larsson-Edefors, Per Stenström
    FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:18-25 [Conf]
  85. Jochen Hollmann, Anders Ardö, Per Stenström
    Effectiveness of caching in a distributed digital library system. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:7, pp:403-416 [Journal]
  86. Jianwei Chen, Michel Dubois, Per Stenström
    SimWattch: Integrating Complete-System and User-Level Performance and Power Simulators. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:4, pp:34-48 [Journal]

  87. Using Hoarding to Increase Availability in Shared File Systems. [Citation Graph (, )][DBLP]


  88. Zero-Value Caches: Cancelling Loads that Return Zero. [Citation Graph (, )][DBLP]


  89. Leveraging Data Promotion for Low Power D-NUCA Caches. [Citation Graph (, )][DBLP]


  90. A Flexible Code Compression Scheme Using Partitioned Look-Up Tables. [Citation Graph (, )][DBLP]


  91. An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors. [Citation Graph (, )][DBLP]


  92. Chip-multiprocessing and beyond. [Citation Graph (, )][DBLP]


  93. Accommodation of the Bandwidth of Large Cache Blocks Using Cache/Memory Link Compression. [Citation Graph (, )][DBLP]


  94. Cancellation of loads that return zero using zero-value caches. [Citation Graph (, )][DBLP]


  95. Intermediate checkpointing with conflicting access prediction in transactional memory systems. [Citation Graph (, )][DBLP]


  96. Enhancing Multiprocessor Architecture Simulation Speed Using Matched-Pair Comparison. [Citation Graph (, )][DBLP]


  97. Efficient management of speculative data in hardware transactional memory systems. [Citation Graph (, )][DBLP]


  98. Scalable Value-Cache Based Compression Schemes for Multiprocessors. [Citation Graph (, )][DBLP]


  99. Dual-Thread Speculation: Two Threads in the Machine are Worth Eight in the Bush. [Citation Graph (, )][DBLP]


  100. Energy and Performance Trade-offs between Instruction Reuse and Trivial Computations for Embedded Applications. [Citation Graph (, )][DBLP]


  101. Schemes for avoiding starvation in transactional memory systems. [Citation Graph (, )][DBLP]


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