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Eric Martin: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Eric Martin
    Quantification over names and modalities. [Citation Graph (0, 0)][DBLP]
    Advances in Modal Logic, 2006, pp:353-372 [Conf]
  2. Sanjay Jain, Eric Martin, Frank Stephan
    Absolute Versus Probabilistic Classification in a Logical Setting. [Citation Graph (0, 0)][DBLP]
    ALT, 2005, pp:327-342 [Conf]
  3. Eric Martin, Arun Sharma, Frank Stephan
    Learning, Logic, and Topology in a Common Framework. [Citation Graph (0, 0)][DBLP]
    ALT, 2002, pp:248-262 [Conf]
  4. Eric Martin, Arun Sharma, Frank Stephan
    On Ordinal VC-Dimension and Some Notions of Complexity. [Citation Graph (0, 0)][DBLP]
    ALT, 2003, pp:54-68 [Conf]
  5. Eric Martin, Arun Sharma, Frank Stephan
    On the Data Consumption Benefits of Accepting Increased Uncertainty. [Citation Graph (0, 0)][DBLP]
    ALT, 2004, pp:83-98 [Conf]
  6. Jane Brennan, Eric Martin
    Foundations for a Formalism of Nearness. [Citation Graph (0, 0)][DBLP]
    Australian Joint Conference on Artificial Intelligence, 2002, pp:71-82 [Conf]
  7. Jane Brennan, Eric Martin
    Membership Functions for Spatial Proximity. [Citation Graph (0, 0)][DBLP]
    Australian Conference on Artificial Intelligence, 2006, pp:942-949 [Conf]
  8. Gwenolé Corre, Eric Senn, Pierre Bomel, Nathalie Julien, Eric Martin
    Memory accesses management during high level synthesis. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:42-47 [Conf]
  9. Eric Martin, Arun Sharma
    On a Syntactic Characterization of Classification with a Mind Change Bound. [Citation Graph (0, 0)][DBLP]
    COLT, 2005, pp:413-428 [Conf]
  10. Adel Baganne, Imed Bennour, Mehrez Elmarzougui, Riadh Gaiech, Eric Martin
    A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:20250-20255 [Conf]
  11. Pierre Bomel, Eric Martin, Emmanuel Boutillon
    Synchronization Processor Synthesis for Latency Insensitive Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:896-897 [Conf]
  12. Johann Laurent, Nathalie Julien, Eric Senn, Eric Martin
    Functional Level Power Analysis: An Efficient Approach for Modeling the Power Consumption of Complex Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:666-667 [Conf]
  13. Tri M. Cao, Eric Martin, Paul Compton
    On the Convergence of Incremental Knowledge Base Construction.. [Citation Graph (0, 0)][DBLP]
    Discovery Science, 2004, pp:207-218 [Conf]
  14. Eric Martin, Arun Sharma, Frank Stephan
    A General Theory of Deduction, Induction, and Learning. [Citation Graph (0, 0)][DBLP]
    Discovery Science, 2001, pp:228-242 [Conf]
  15. David Elléouet, Nathalie Julien, Dominique Houzet, J.-G. Cousin, Eric Martin
    Power Consumption Characterization and Modeling of Embedded Memories in XILINX VIRTEX 400E FPGA. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:394-401 [Conf]
  16. Pierre Bomel, Nabil Abdelli, Eric Martin, A.-M. Fouilliart, Emmanuel Boutillon, Philippe Kajfasz
    High-Level Synthesis in Latency Insensitive System Methodology. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:96-101 [Conf]
  17. Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin
    Memory Aware HLS and the Implementation of Ageing Vectors. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:88-95 [Conf]
  18. Florian Marteil, Nathalie Julien, Eric Senn, Eric Martin
    A Complete Methodology for Memory Optimization in DSP Applications. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:98-103 [Conf]
  19. Eric Martin, Daniel N. Osherson
    A note on the use of probabilities by mechanical learners. [Citation Graph (0, 0)][DBLP]
    EuroCOLT, 1995, pp:261-271 [Conf]
  20. Adel Baganne, Jean Luc Philippe, Eric Martin
    Hardware interface design for real time embedded systems. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1997, pp:58-63 [Conf]
  21. Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin
    A memory aware behavioral synthesis tool for real-time VLSI circuits. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:82-85 [Conf]
  22. S. Gailhard, Nathalie Julien, Adel Baganne, Eric Martin
    Low Power Design of an Acoustic Echo Canceller Gmdf a Algorithm on Dedicated VLSI Architectures. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:334-335 [Conf]
  23. S. Gailhard, Nathalie Julien, Jean-Philippe Diguet, Eric Martin
    How to Transform an Architectural Synthesis Tool for Low Power VLSI Designs. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:426-0 [Conf]
  24. Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
    A design methodology for space-time adapter. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:347-352 [Conf]
  25. John Case, Sanjay Jain, Eric Martin, Arun Sharma, Frank Stephan
    Identifying Clusters from Positive Data. [Citation Graph (0, 0)][DBLP]
    ICGI, 2004, pp:103-114 [Conf]
  26. Patrick Caldon, Eric Martin
    Limiting Resolution: From Foundations to Implementation. [Citation Graph (0, 0)][DBLP]
    ICLP, 2004, pp:149-164 [Conf]
  27. Eric Martin, Phuong Nguyen, Arun Sharma, Frank Stephan
    Learning in Logic with RichProlog. [Citation Graph (0, 0)][DBLP]
    ICLP, 2002, pp:239-254 [Conf]
  28. Eric Senn, Eric Martin
    A Vision System on Chip for Industrial Control. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:27-38 [Conf]
  29. Christophe Jégo, Emmanuel Casseau, Eric Martin
    Architectural Synthesis with Interconnection Cost Control. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:509-520 [Conf]
  30. Eric Martin, Arun Sharma
    On Sufficient Conditions for Learnability of Logic Programs from Positive Data. [Citation Graph (0, 0)][DBLP]
    ILP, 1999, pp:198-209 [Conf]
  31. Emmanuel Casseau, Bertrand Le Gal, Christophe Jégo, Nathalie Le Heno, Eric Martin
    Reed-Solomon behavioral virtual component for communication systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:173-176 [Conf]
  32. Philippe Coussy, Gwenolé Corre, Eric Senn, Pierre Bomel, Eric Martin
    High-level synthesis under I/O timing and memory constraints. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:680-683 [Conf]
  33. Philippe Coussy, Adel Baganne, Eric Martin
    A design methodology for IP integration. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:711-714 [Conf]
  34. Nathalie Julien, Johann Laurent, Eric Senn, Eric Martin
    Power Estimation of a C Algorithm Based on the Functional-Level Power Analysis of a Digital Signal Processor. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2002, pp:354-360 [Conf]
  35. Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin
    A Memory Aware High Level Synthesis Tool . [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:279-280 [Conf]
  36. Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet, Eric Martin
    Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:268-269 [Conf]
  37. Eric Senn, Nathalie Julien, Johann Laurent, Eric Martin
    Power Consumption Estimation of a C Program for Data-Intensive Applications. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:332-341 [Conf]
  38. Eric Senn, Johann Laurent, Nathalie Julien, Eric Martin
    SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:342-351 [Conf]
  39. Pierre Bomel, Nabil Abdelli, Eric Martin, A.-M. Fouilliart, Emmanuel Boutillon, Philippe Kajfasz
    DVB-DSNG Modem High Level Synthesis in an Optimized Latency Insensitive System Context. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2005, pp:424-433 [Conf]
  40. Philippe Coussy, Adel Baganne, Eric Martin
    Communication and Timing Constraints Analysis for IP Design and Integration. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:38-43 [Conf]
  41. John Case, Sanjay Jain, Eric Martin, Arun Sharma, Frank Stephan
    Identifying Clusters from Positive Data [Citation Graph (0, 0)][DBLP]
    Electronic Colloquium on Computational Complexity (ECCC), 2004, v:, n:058, pp:- [Journal]
  42. Eric Martin, Daniel N. Osherson
    Induction by Enumeration. [Citation Graph (0, 0)][DBLP]
    Inf. Comput., 2001, v:171, n:1, pp:50-68 [Journal]
  43. Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin
    Constrained algorithmic IP design for system-on-chip. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:2, pp:94-105 [Journal]
  44. Eric Martin, Alex Wong
    Sensitivity Analysis and Other Improvements to Tailored Combinatorial Library Design. [Citation Graph (0, 0)][DBLP]
    Journal of Chemical Information and Computer Sciences, 2000, v:40, n:2, pp:215-220 [Journal]
  45. Eric Martin, Daniel N. Osherson
    Scientific Discovery Based on Belief Revision. [Citation Graph (0, 0)][DBLP]
    J. Symb. Log., 1997, v:62, n:4, pp:1352-1370 [Journal]
  46. Nathalie Julien, Johann Laurent, Eric Senn, Eric Martin
    Power Consumption Modeling and Characterization of the TI C6201. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:5, pp:40-49 [Journal]
  47. John Case, Sanjay Jain, Eric Martin, Arun Sharma, Frank Stephan
    Identifying Clusters from Positive Data. [Citation Graph (0, 0)][DBLP]
    SIAM J. Comput., 2006, v:36, n:1, pp:28-55 [Journal]
  48. Eric Martin, Arun Sharma, Frank Stephan
    Learning power and language expressiveness. [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 2003, v:2, n:298, pp:365-383 [Journal]
  49. Eric Martin, Arun Sharma, Frank Stephan
    Unifying logic, topology and learning in Parametric logic. [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 2006, v:350, n:1, pp:103-124 [Journal]
  50. Eric Martin, Arun Sharma, Frank Stephan
    On ordinal VC-dimension and some notions of complexity. [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 2006, v:364, n:1, pp:62-76 [Journal]
  51. Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin
    A formal method for hardware IP design and integration under I/O and timing constraints. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:1, pp:29-53 [Journal]
  52. Emmanuel Casseau, Christophe Jégo, Eric Martin
    Synthèse architecturale d'applications temps réel pour technologies submicroniques. [Citation Graph (0, 0)][DBLP]
    Technique et Science Informatiques, 2004, v:23, n:1, pp:35-66 [Journal]
  53. Guillaume Savaton, Emmanuel Casseau, Eric Martin
    Design of a flexible 2-D discrete wavelet transform IP core for JPEG2000 image coding in embedded imaging systems. [Citation Graph (0, 0)][DBLP]
    Signal Processing, 2006, v:86, n:7, pp:1375-1399 [Journal]
  54. Sanjay Jain, Eric Martin, Frank Stephan
    Input-Dependence in Function-Learning. [Citation Graph (0, 0)][DBLP]
    CiE, 2007, pp:378-388 [Conf]
  55. Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
    A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2946-2949 [Conf]
  56. Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
    A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  57. Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
    A Design Methodology for Space-Time Adapter [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  58. Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
    Méthodologie de modélisation et d'implémentation d'adaptateurs spatio-temporels [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  59. Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin
    Application of a design space exploration tool to enhance interleaver generation [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  60. Gwenolé Corre, Nathalie Julien, Eric Senn, Eric Martin
    Intégration de la synthèse mémoire dans l'outil de synthèse d'architecture GAUT Low Power [Citation Graph (0, 0)][DBLP]
    CoRR, 2006, v:0, n:, pp:- [Journal]
  61. Philippe Coussy, Gwenolé Corre, Pierre Bomel, Eric Senn, Eric Martin
    High-level synthesis under I/O Timing and Memory constraints [Citation Graph (0, 0)][DBLP]
    CoRR, 2006, v:0, n:, pp:- [Journal]
  62. Gwenolé Corre, Nathalie Julien, Eric Senn, Eric Martin
    A Memory Aware High Level Synthesis Too [Citation Graph (0, 0)][DBLP]
    CoRR, 2006, v:0, n:, pp:- [Journal]
  63. Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin
    Memory Aware High-Level Synthesis for Embedded Systems [Citation Graph (0, 0)][DBLP]
    CoRR, 2006, v:0, n:, pp:- [Journal]
  64. Gwenolé Corre, Philippe Coussy, Pierre Bomel, Eric Senn, Eric Martin
    Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSI [Citation Graph (0, 0)][DBLP]
    CoRR, 2006, v:0, n:, pp:- [Journal]
  65. Pierre Bomel, Eric Martin, Emmanuel Boutillon
    Synchronization Processor Synthesis for Latency Insensitive Systems [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  66. Eric Martin, Arun Sharma, Frank Stephan
    On the data consumption benefits of accepting increased uncertainty. [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 2007, v:382, n:3, pp:170-182 [Journal]
  67. Fatma Sayadi, Emmanuel Casseau, Mohamed Atri, Mehrez Marzougui, Rached Tourki, Eric Martin
    G729 Voice Decoder Design. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:42, n:2, pp:173-184 [Journal]

  68. A design flow dedicated to multi-mode architectures for DSP applications. [Citation Graph (, )][DBLP]


  69. Autonomous Capture of a Tumbling Satellite. [Citation Graph (, )][DBLP]


  70. SystemCmantic: A high level Modelling and Co-Design Framework. [Citation Graph (, )][DBLP]


  71. Design Space Exploration of DSP Applications Based on Behavioral Description Models. [Citation Graph (, )][DBLP]


  72. Static Address Generation Easing: a Design Methodology for Parallel Interleaver Architectures [Citation Graph (, )][DBLP]


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