Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2005, volume: 24, number: 12

1. Ivan Augé, Frédéric Pétrot, François Donnet, Pascal Gomez
   Platform-based design from parallel C specifications. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:12, pp:1811-1826 [Journal]
   
2. Lin Yuan, Gang Qu
   Analysis of energy reduction on dynamic voltage scaling-enabled systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:12, pp:1827-1837 [Journal]
   
3. Lihong Feng, Evgenii B. Rudnyi, Jan G. Korvink
   Preserving the film coefficient as a parameter in the compact thermal model for fast electrothermal simulation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:12, pp:1838-1847 [Journal]
   
4. Joon-Ho Lee, Qing Huo Liu
   An efficient 3-D spectral-element method for Schro/spl uml/dinger equation in nanodevice simulation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:12, pp:1848-1858 [Journal]
   
5. Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy
   Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:12, pp:1859-1880 [Journal]
   
6. Mariam Momenzadeh, Jing Huang, Mehdi Baradaran Tahoori, Fabrizio Lombardi
   Characterization, test, and logic synthesis of and-or-inverter (AOI) gate design for QCA implementation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:12, pp:1881-1893 [Journal]
   
7. Qiang Xu, Nicola Nicolici
   Modular SOC testing with reduced wrapper count. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:12, pp:1894-1908 [Journal]
   
8. Sandip Kundu, Sujit T. Zachariah, Yi-Shing Chang, Chandra Tirumurti
   On modeling crosstalk faults. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:12, pp:1909-1915 [Journal]
   
9. Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng
   Power-optimal simultaneous buffer insertion/sizing and wire sizing for two-pin nets. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:12, pp:1915-1924 [Journal]
   
10. Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
    Longest-path selection for delay test under process variation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:12, pp:1924-1929 [Journal]
    
11. Patrick Schaumont, David Hwang, Ingrid Verbauwhede
    Platform-based design for an embedded-fingerprint-authentication device. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:12, pp:1929-1936 [Journal]
    
12. A. Prasad Vinod, Edmund Ming-Kit Lai
    An efficient coefficient-partitioning algorithm for realizing low-complexity digital filters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:12, pp:1936-1946 [Journal]