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## Search the dblp DataBase
Dian Zhou:
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## Publications of Author- Ruiming Li, Dian Zhou, Donglei Du
**Satisfiability and integer programming as complementary tools.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2004, pp:879-882 [Conf] - Bang Liu, Xuan Zeng, Yangfeng Su, Jun Tao, Zhaojun Bai, Charles Chiang, Dian Zhou
**Block SAPOR: block Second-order Arnoldi method for Passive Order Reduction of multi-input multi-output RCS interconnect circuits.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:244-249 [Conf] - Jian Wang, Jun Tao, Xuan Zeng, Charles Chiang, Dian Zhou
**Analog circuit behavioral modeling via wavelet collocation method with auto-companding.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2004, pp:45-50 [Conf] - Xuan Zeng, Bank Liu, Jun Tao, Charles Chiang, Dian Zhou
**A novel wavelet method for noise analysis of nonlinear circuits.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:471-476 [Conf] - Jason Cong, Kwok-Shing Leung, Dian Zhou
**Performance-Driven Interconnect Design Based on Distributed RC Delay Model.**[Citation Graph (0, 0)][DBLP] DAC, 1993, pp:606-611 [Conf] - Lihong Feng, Xuan Zeng, Charles Chiang, Dian Zhou, Qiang Fang
**Direct Nonlinear Order Reduction with Variational Analysis.**[Citation Graph (0, 0)][DBLP] DATE, 2004, pp:1316-1321 [Conf] - Xuan Zeng, Lihong Feng, Yangfeng Su, Wei Cai, Dian Zhou, Charles Chiang
**Time domain model order reduction by wavelet collocation method.**[Citation Graph (0, 0)][DBLP] DATE, 2006, pp:21-26 [Conf] - Xin Zhou, Dian Zhou, Jin Liu, Ruiming Li, Xuan Zeng, Charles Chiang
**Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method.**[Citation Graph (0, 0)][DBLP] DATE, 2004, pp:1322-1326 [Conf] - Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng
**Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing.**[Citation Graph (0, 0)][DBLP] ICCAD, 2003, pp:581-587 [Conf] - Xin Li, Xuan Zeng, Dian Zhou, Xieting Ling
**Behavioral Modeling of Analog Circuits by Wavelet Collocation Method.**[Citation Graph (0, 0)][DBLP] ICCAD, 2001, pp:65-69 [Conf] - Yangfeng Su, Jian Wang, Xuan Zeng, Zhaojun Bai, Charles Chiang, Dian Zhou
**SAPOR: second-order Arnoldi method for passive order reduction of RCS circuits.**[Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:74-79 [Conf] - Dian Zhou, F. Tsui
**Neighbour State Transition Method for VLSI Optimization Problems.**[Citation Graph (0, 0)][DBLP] ICCD, 1993, pp:476-479 [Conf] - Nisar Ahmed, Mohammad H. Tehranipour, Dian Zhou, Mehrdad Nourani
**Frequency driven repeater insertion for deep submicron.**[Citation Graph (0, 0)][DBLP] ISCAS (5), 2004, pp:181-184 [Conf] - Zhongli He, Dian Zhou
**Optimization of VLSI Allocation.**[Citation Graph (0, 0)][DBLP] ISCAS, 1995, pp:1065-1068 [Conf] - Lihong Feng, Xuan Zeng, Jiarong Tong, Charles Chiang, Dian Zhou
**Two-sided projection method in variational equation model order reduction of nonlinear circuits.**[Citation Graph (0, 0)][DBLP] ISCAS (4), 2004, pp:816-819 [Conf] - D. S. Gao, Dian Zhou
**Propagation Delay in RLC Interconnection Networks.**[Citation Graph (0, 0)][DBLP] ISCAS, 1993, pp:2125-2128 [Conf] - Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng
**Power-optimal simultaneous buffer insertion/sizing and uniform wire sizing for single long wires.**[Citation Graph (0, 0)][DBLP] ISCAS (1), 2005, pp:113-116 [Conf] - Jian Wang, Xuan Zeng, Wei Cai, Charles Chiang, Jiarong Tong, Dian Zhou
**Frequency domain wavelet method with GMRES for large-scale linear circuit simulation.**[Citation Graph (0, 0)][DBLP] ISCAS (5), 2004, pp:321-324 [Conf] - Xuan Zeng, Sheng Huang, Yangfeng Su, Dian Zhou
**An efficient Sylvester equation solver for time domain circuit simulation by wavelet collocation method.**[Citation Graph (0, 0)][DBLP] ISCAS (4), 2003, pp:664-667 [Conf] - Xuan Zeng, Jun Tao, Yangfeng Su, Wenbing Chen, Dian Zhou
**An error distribution based nonlinear companding method for analog behavioral modeling via wavelet approximation.**[Citation Graph (0, 0)][DBLP] ISCAS (3), 2003, pp:168-171 [Conf] - Hua Zhang, Dian Zhou, Yi Hu, Ruiming Li, Jianzhong Zhang
**Phase noise spectra analysis for LC oscillators.**[Citation Graph (0, 0)][DBLP] ISCAS (3), 2005, pp:2263-2266 [Conf] - Hua Zhang, Jianzhong Zhang, Dian Zhou, Jin Liu, Liangjun Jiang, Yan Pan
**A closed-form phase noise solution for an ideal LC oscillator.**[Citation Graph (0, 0)][DBLP] ISCAS (4), 2004, pp:768-771 [Conf] - Dian Zhou, S. Su, F. Tsui, D. S. Gao, Jason Cong
**A Two-pole Circuit Model for VLSI High-speed Interconnection.**[Citation Graph (0, 0)][DBLP] ISCAS, 1993, pp:2129-2132 [Conf] - Haksu Kim, Dian Zhou
**An automatic clock tree design system for high-speed VLSI designs: planar clock routing with the treatment of obstacles.**[Citation Graph (0, 0)][DBLP] ISCAS (6), 1999, pp:258-261 [Conf] - Xin Li, Xuan Zeng, Dian Zhou, Xieting Ling
**Wavelet method for high-speed clock tree simulation.**[Citation Graph (0, 0)][DBLP] ISCAS (1), 2002, pp:177-180 [Conf] - Ronald W. Mehler, Dian Zhou
**Automated Architectural Optimization of Digital FIR Filters.**[Citation Graph (0, 0)][DBLP] VLSI Design, 2004, pp:177-182 [Conf] - Dian Zhou, Ruiming Li
**Design and Verification of High-Speed VLSI Physical Design.**[Citation Graph (0, 0)][DBLP] J. Comput. Sci. Technol., 2005, v:20, n:2, pp:147-165 [Journal] - Haksu Kim, Dian Zhou
**Efficient implementation of a planar clock routing with thetreatment of obstacles.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:10, pp:1220-1225 [Journal] - Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng
**Power-optimal simultaneous buffer insertion/sizing and wire sizing for two-pin nets.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:12, pp:1915-1924 [Journal] - Sanjeev Rao Maddila, Dian Zhou
**Routing in general junctions.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:11, pp:1174-1184 [Journal] - Xiaoyu Song, Qian-Yu Tang, Dian Zhou, Yuke Wang
**Wire space estimation and routability analysis.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:5, pp:624-628 [Journal] - Wei Li, Daniel Blakely, Scott Van Sooy, Keven Dunn, David Kidd, Robert Rogenmoser, Dian Zhou
**LVS verification across multiple power domains for a quad-core microprocessor.**[Citation Graph (0, 0)][DBLP] ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:2, pp:490-500 [Journal] - Hengliang Zhu, Xuan Zeng, Wei Cai, Jintao Xue, Dian Zhou
**A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology.**[Citation Graph (0, 0)][DBLP] DATE, 2007, pp:1514-1519 [Conf] - Fan Yang, Xuan Zeng, Yangfeng Su, Dian Zhou
**RLCSYN: RLC Equivalent Circuit Synthesis for Structure-Preserved Reduced-order Model of Interconnect.**[Citation Graph (0, 0)][DBLP] ISCAS, 2007, pp:2710-2713 [Conf] - Jun Tao, Xuan Zeng, Fan Yang, Yangfeng Su, Lihong Feng, Wei Cai, Dian Zhou, Charles Chiang
**A one-shot projection method for interconnects with process variations.**[Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf] **Stochastic Sparse-grid Collocation Algorithm (SSCA) for Periodic Steady-State Analysis of Nonlinear System with Process Variations.**[Citation Graph (, )][DBLP]**Foundational-circuit-based spice simulation.**[Citation Graph (, )][DBLP]**Analytical Evaluation of Retransmission Schemes in Wireless Sensor Networks.**[Citation Graph (, )][DBLP]**A Spectral Stochastic Collocation Method for Capacitance Extraction of Interconnects with Process Variations.**[Citation Graph (, )][DBLP]**Traffic Splitting with Network Calculus for Mesh Sensor Networks.**[Citation Graph (, )][DBLP]
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