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Sandip Kundu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Anirudh Devgan, Sandip Kundu
    Timing Analysis and Optimization: From Devices to Systems (Abstract of Embedded Tutorial). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:345- [Conf]
  2. Jing-Jia Liou, Angela Krstic, Kwang-Ting Cheng, Deb Aditya Mukherjee, Sandip Kundu
    Performance sensitivity analysis using statistical method and its applications to delay. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:587-592 [Conf]
  3. Vishwani D. Agrawal, Bernard Courtois, Fumiyasu Hirose, Sandip Kundu, Chung-Len Lee, Yinghua Min, P. Pal Chaudhuri
    Panel: New Research Problems in the Emerging Test Technology. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:189-0 [Conf]
  4. Sandip Kundu
    IDDQ Defect Detection in Deep Submicron CMOS ICs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:150-152 [Conf]
  5. Sandip Kundu, Piet Engelke, Ilia Polian, Bernd Becker
    On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:266-271 [Conf]
  6. Jacob A. Abraham, Sandip Kundu, Janak H. Patel, Manuel A. d'Abreu, Bulent I. Dervisoglu, Marc E. Levitt, Hector R. Sucar, Ron G. Walther
    Microprocessor Testing: Which Technique is Best? (Panel). [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:294- [Conf]
  7. Jing-Jia Liou, Kwang-Ting Cheng, Sandip Kundu, Angela Krstic
    Fast Statistical Timing Analysis By Probabilistic Event Propagation. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:661-666 [Conf]
  8. Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy
    On output response compression in the presence of unknown output values. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:255-258 [Conf]
  9. Bill Grundmann, Rajesh Galivanche, Sandip Kundu
    Circuit and Platform Design Challenges in Technologies beyond 90nm. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10044-10049 [Conf]
  10. Sandip Kundu
    A design for failure analysis (DFFA) technique to ensure incorruptible signatures. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:309-310 [Conf]
  11. Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
    On the Characterization of Hard-to-Detect Bridging Faults. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11012-11019 [Conf]
  12. Chandra Tirumurti, Sandip Kundu, Susmita Sur-Kolay, Yi-Shing Chang
    A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1078-1083 [Conf]
  13. Sujit T. Zachariah, Yi-Shing Chang, Sandip Kundu, Chandra Tirumurti
    On Modeling Cross-Talk Faults. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10490-10495 [Conf]
  14. Daniel Brand, Anthony D. Drumm, Sandip Kundu, Prakash Narain
    Incremental synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:14-18 [Conf]
  15. Anirudh Devgan, Leon Stok, Sandip Kundu
    Timing analysis and optimization: from devices to systems (tutorial). [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:- [Conf]
  16. Rob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, Sandip Kundu
    Static statistical timing analysis for latch-based pipeline designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:468-472 [Conf]
  17. Sandip Kundu
    Multifault Testable Circuits Based on Binary Parity Diagrams. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:363-366 [Conf]
  18. Sreenivas Mandava, Sreejit Chakravarty, Sandip Kundu
    On Detecting Bridges Causing Timing Failures. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:400-406 [Conf]
  19. Sandip Kundu, Ilia Polian
    An Improved Technique for Reducing False Alarms Due to Soft Errors. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:105-110 [Conf]
  20. Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu
    On Accelerating Soft-Error Detection by Targeted Pattern Generation. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:723-728 [Conf]
  21. Sandip Kundu
    GateMaker: a transistor to gate level model extractor for simulation, automatic test pattern generation and verification. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:372-0 [Conf]
  22. Sandip Kundu, Leendert M. Huisman, Indira Nair, Vijay S. Iyengar, Lakshmi N. Reddy
    A Small Test Generator for Large Designs. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:30-40 [Conf]
  23. Sandip Kundu, T. M. Mak, Rajesh Galivanche
    Trends in manufacturing test methods and their implications. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:679-687 [Conf]
  24. Sandip Kundu, Sudhakar M. Reddy
    Robust Tests for Parity Trees. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:680-687 [Conf]
  25. Masao Naruse, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
    On-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1060-1068 [Conf]
  26. Ankan K. Pramanick, Sandip Kundu
    Design of Scan-Based Path-Delay-Testable Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:962-971 [Conf]
  27. Debasis Mitra, Subhasis Bhattacharjee, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sujit T. Zachariah, Sandip Kundu
    Test Pattern Generation for Power Supply Droop Faults. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:343-348 [Conf]
  28. Sitaram Yadavalli, Sandip Kundu
    On Fault-Simulation Through Embedded Memories On Large Industrial Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:117-121 [Conf]
  29. Ashesh Rastogi, Wei Chen, Alodeep Sanyal, Sandip Kundu
    An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:583-588 [Conf]
  30. Ilia Polian, Sandip Kundu, Jean Marc Galliere, Piet Engelke, Michel Renovell, Bernd Becker
    Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:343-348 [Conf]
  31. Rob Aitken, Stefan Eichenberger, Gary Maier, Sandip Kundu, Hank Walker
    ITC 2003 Roundtable: Design for Manufacturability. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:2, pp:144-156 [Journal]
  32. Sandip Kundu
    TTTC technical forum honoring Sudhakar M. Reddy. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:2, pp:167- [Journal]
  33. Sandip Kundu, Sudhakar M. Reddy
    Embedded Totally Self-Checking Checkers: A Practical Design. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1990, v:7, n:4, pp:5-12 [Journal]
  34. Sandip Kundu, Sudhakar M. Reddy
    On Symmetric Error Correcting and All Unidirectional Error Detecting Codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:6, pp:752-761 [Journal]
  35. Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy
    Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:1, pp:83-88 [Journal]
  36. Sandip Kundu
    Pitfalls of hierarchical fault simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:312-314 [Journal]
  37. Sandip Kundu
    Design of multioutput CMOS combinational logic circuits for robust testability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:11, pp:1222-1226 [Journal]
  38. Sandip Kundu, Sudhakar M. Reddy, Niraj K. Jha
    Design of robustly testable combinational logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:8, pp:1036-1048 [Journal]
  39. Sandip Kundu, Sujit T. Zachariah, Yi-Shing Chang, Chandra Tirumurti
    On modeling crosstalk faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:12, pp:1909-1915 [Journal]
  40. Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
    On the characterization and efficient computation of hard-to-detect bridging faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1640-1649 [Journal]
  41. Leendert M. Huisman, Sandip Kundu
    Highly Reliable Symmetric Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1994, v:5, n:1, pp:94-97 [Journal]
  42. Ashesh Rastogi, Wei Chen, Sandip Kundu
    On Estimating Impact of Loading Effect on Leakage Current in Sub-65nm Scaled CMOS Circuits Based on Newton-Raphson Method. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:712-715 [Conf]
  43. Kunal P. Ganeshpure, Sandip Kundu
    Interactive presentation: Automatic test pattern generation for maximal circuit noise in multiple aggressor crosstalk faults. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:540-545 [Conf]
  44. Alodeep Sanyal, Sandip Kundu
    On Derating Soft Error Probability Based on Strength Filtering. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:152-160 [Conf]
  45. Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu
    Accelerating Soft Error Rate Testing Through Pattern Selection. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:191-193 [Conf]
  46. Ashesh Rastogi, Kunal P. Ganeshpure, Sandip Kundu
    A Study on Impact of Leakage Current on Dynamic Power. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1069-1072 [Conf]

  47. On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits. [Citation Graph (, )][DBLP]

  48. Inductance analysis of on-chip interconnects [deep submicron CMOS]. [Citation Graph (, )][DBLP]

  49. A study on placement of post silicon clock tuning buffers for mitigating impact of process variation. [Citation Graph (, )][DBLP]

  50. Improving yield and reliability of chip multiprocessors. [Citation Graph (, )][DBLP]

  51. A self-adaptive system architecture to address transistor aging. [Citation Graph (, )][DBLP]

  52. On linewidth-based yield analysis for nanometer lithography. [Citation Graph (, )][DBLP]

  53. Hardware/software co-design architecture for thermal management of chip multiprocessors. [Citation Graph (, )][DBLP]

  54. The Guiding Light for Chip Testing. [Citation Graph (, )][DBLP]

  55. Core Test Wrapper Design to Reduce Test Application Time for Modular SoC Testing. [Citation Graph (, )][DBLP]

  56. A Low Cost Scheme for Reducing Silent Data Corruption in Large Arithmetic Circuit. [Citation Graph (, )][DBLP]

  57. On process variation tolerant low cost thermal sensor design in 32nm CMOS technology. [Citation Graph (, )][DBLP]

  58. A process variation tolerant self-compensating FinFET based sense amplifier design. [Citation Graph (, )][DBLP]

  59. A study on impact of aggressor de-rating in the context of multiple crosstalk effects in circuits. [Citation Graph (, )][DBLP]

  60. Process variation mitigation via post silicon clock tuning. [Citation Graph (, )][DBLP]

  61. Reducing temperature variability by routing heat pipes. [Citation Graph (, )][DBLP]

  62. TURBONFS: turbo nand flash search. [Citation Graph (, )][DBLP]

  63. A model to exploit power-performance efficiency in superscalar processors via structure resizing. [Citation Graph (, )][DBLP]

  64. A self-adaptive scheduler for asymmetric multi-cores. [Citation Graph (, )][DBLP]

  65. A mask double patterning technique using litho simulation by wavelet transform. [Citation Graph (, )][DBLP]

  66. Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines. [Citation Graph (, )][DBLP]

  67. A framework for predictive dynamic temperature management of microprocessor systems. [Citation Graph (, )][DBLP]

  68. On modeling impact of sub-wavelength lithography on transistors. [Citation Graph (, )][DBLP]

  69. A Pattern Generation Technique for Maximizing Power Supply Currents. [Citation Graph (, )][DBLP]

  70. Power Droop Testing. [Citation Graph (, )][DBLP]

  71. Modeling and analysis of non-rectangular transistors caused by lithographic distortions. [Citation Graph (, )][DBLP]

  72. A Built-In Self-Test Scheme for Soft Error Rate Characterization. [Citation Graph (, )][DBLP]

  73. A Built-in Test and Characterization Method for Circuit Marginality Related Failures. [Citation Graph (, )][DBLP]

  74. A study on impact of loading effect on capacitive crosstalk noise. [Citation Graph (, )][DBLP]

  75. On Common-Mode Skewed-Load and Broadside Tests. [Citation Graph (, )][DBLP]

  76. An ILP Based ATPG Technique for Multiple Aggressor Crosstalk Faults Considering the Effects of Gate Delays. [Citation Graph (, )][DBLP]

  77. Optical Lithography Simulation with Focus Variation using Wavelet Transform. [Citation Graph (, )][DBLP]

  78. Power Droop Testing. [Citation Graph (, )][DBLP]

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