Journals in DBLP

IEEE Trans. VLSI Syst.
2003, volume: 11, number: 2

1. David Blaauw, Supamas Sirichotiyakul, Chanhee Oh
   Driver modeling and alignment for worst-case delay noise. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:2, pp:157-166 [Journal]
   
2. K. Chakrabarty
   A synthesis-for-transparency approach for hierarchical and system-on-a-chip test. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:2, pp:167-179 [Journal]
   
3. Payam Heydari, Massoud Pedram
   Ground bounce in digital VLSI circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:2, pp:180-193 [Journal]
   
4. Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou
   A true single-phase energy-recovery multiplier. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:2, pp:194-207 [Journal]
   
5. Surin Kittitornkun, Yu Hen Hu
   Mapping deep nested do-loop DSP algorithms to large scale FPGA array structures. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:2, pp:208-217 [Journal]
   
6. Kyung-suc Nah, Byeong-ha Park
   A 50-MHz dB-linear programmable-gain amplifier with 98-dB dynamic range and 2-dB gain steps for 3 V power supply. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:2, pp:218-223 [Journal]
   
7. Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
   Maximizing throughput over parallel wire structures in the deep submicrometer regime. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:2, pp:224-243 [Journal]
   
8. Jongsun Park, Khurram Muhammad, Kaushik Roy
   High-performance FIR filter design based on sharing multiplication. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:2, pp:244-253 [Journal]
   
9. Lei Wang, Naresh R. Shanbhag
   Energy-efficiency bounds for deep submicron VLSI systems in the presence of noise. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:2, pp:254-269 [Journal]
   
10. Ali Manzak, Chaitali Chakrabarti
    Variable voltage task scheduling algorithms for minimizing energy/power. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:2, pp:270-276 [Journal]
    
11. R. Hossain, F. Viglione, M. Cavalli
    Designing fast on-chip interconnects for deep submicrometer technologies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:2, pp:276-280 [Journal]
    
12. Uwe Meyer-Bäse, Thanos Stouraitis
    New power-of-2 RNS scaling scheme for cell-based IC design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:2, pp:280-283 [Journal]
    
13. Abdel Ejnioui, N. Ranganathan
    Routing on field-programmable switch matrices. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:2, pp:283-287 [Journal]
    
14. Hanho Lee
    High-speed VLSI architecture for parallel Reed-Solomon decoder. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:2, pp:288-294 [Journal]
    
15. D. Harris, S. Naffziger
    Correction to "statistical clock skew modeling with data delay variations". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:2, pp:295-296 [Journal]