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Juan Lanchares: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Oscar Garnica, Juan Lanchares, Román Hermida
    Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation. [Citation Graph (0, 0)][DBLP]
    ACSD, 2001, pp:167-178 [Conf]
  2. Oscar Garnica, Juan Lanchares, Román Hermida
    A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:810- [Conf]
  3. Juan de Vicente, Juan Lanchares, Román Hermida
    FPGA Placement by Thermodynamic Combinatorial Optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:54-60 [Conf]
  4. José Ignacio Hidalgo, Juan Lanchares, Aitor Ibarra, Román Hermida
    A Hybrid Evolutionary Algorithm for Multi-FPGA Systems Design. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:60-69 [Conf]
  5. Aitor Ibarra, Juan Lanchares, José Ignacio Hidalgo, F. Saenz
    Pipelined Genetic Architecture with Fitness on the Fly. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:382-385 [Conf]
  6. Aitor Ibarra, José M. Mendías, Juan Lanchares, José Ignacio Hidalgo, Román Hermida
    Optimization of Equational Specifications Using Genetic Techniques. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:252-258 [Conf]
  7. Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar
    A Power-Aware Technique for Functional Units in High-Performance Processors. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:456-459 [Conf]
  8. José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López
    Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:423-432 [Conf]
  9. Aitor Ibarra, Juan Lanchares, Jose Manuel Mendias, José Ignacio Hidalgo, Román Hermida
    Transformation of Equational Specification by Means of Genetic Programming. [Citation Graph (0, 0)][DBLP]
    EuroGP, 2002, pp:248-257 [Conf]
  10. José Ignacio Hidalgo, Juan Lanchares
    Functional Partitioning for Hardware-Software Codesign using Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1997, pp:631-638 [Conf]
  11. José Ignacio Hidalgo, Juan Lanchares, Román Hermida
    Partitioning and Placement for Multi-FPGA Systems Using Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1204-1211 [Conf]
  12. Juan de Vicente, Juan Lanchares, Román Hermida
    RSR: A New Rectilinear Steiner Minimum Tree Approximation for FPGA Placement and Global Routing. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10192-10195 [Conf]
  13. José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López
    Sim-async: An Architectural Simulator for Asynchronous Processor Modeling Using Distribution Functions. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2006, pp:495-505 [Conf]
  14. Juan de Vicente, Juan Lanchares, Román Hermida
    Placement Optimization Based on Global Routing Updating for System Partitioning onto Multi-FPGA Mesh Topologies. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:91-100 [Conf]
  15. José Ignacio Hidalgo, Francisco Fernández de Vega, Juan Lanchares, Juan Manuel Sánchez-Pérez, Román Hermida, Marco Tomassini, Ranieri Baraglia, Raffaele Perego, Oscar Garnica
    Multi-FPGA Systems Synthesis by Means of Evolutionary Computation. [Citation Graph (0, 0)][DBLP]
    GECCO, 2003, pp:2109-2120 [Conf]
  16. Oscar Garnica, Juan Lanchares, Román Hermida
    A New Methodology to Design Low-Power Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:108-117 [Conf]
  17. Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar
    Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:40-48 [Conf]
  18. Guadalupe Miñana, José Ignacio Hidalgo, Oscar Garnica, Juan Lanchares, José Manuel Colmenar, Sonia López
    A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:514-523 [Conf]
  19. Sonia López, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, Román Hermida
    Power-Consumption RRRRreduction in Asynchronous Circuits Using Delay Path Unequalization. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:151-160 [Conf]
  20. José Manuel Colmenar, Oscar Garnica, Sonia López, José Ignacio Hidalgo, Juan Lanchares, Román Hermida
    Empirical Characterization of the Latency of Long Asynchronous Pipelines with Data-Dependent Module Delays. [Citation Graph (0, 0)][DBLP]
    PDP, 2004, pp:112-119 [Conf]
  21. José Ignacio Hidalgo, Manuel Prieto, Juan Lanchares, Ranieri Baraglia, Francisco Tirado, Oscar Garnica
    Hybrid Parallelization of a Compact Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
    PDP, 2003, pp:449-455 [Conf]
  22. José Ignacio Hidalgo, Manuel Prieto, Juan Lanchares, Francisco Tirado, B. de Andrés, S. Esteban, D. Rivera
    A Method for Model Parameter Identification Using Parallel Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    PVM/MPI, 1999, pp:291-298 [Conf]
  23. Juan de Vicente, Juan Lanchares, Román Hermida
    Adaptive FPGA Placement by Natural Optimization. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:188-193 [Conf]
  24. Oscar Garnica, Juan Lanchares, Román Hermida
    Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation. [Citation Graph (0, 0)][DBLP]
    Fundam. Inform., 2002, v:50, n:2, pp:155-174 [Journal]
  25. Juan de Vicente, Juan Lanchares, Román Hermida
    Annealing placement by thermodynamic combinatorial optimization. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2004, v:9, n:3, pp:310-332 [Journal]
  26. Francisco Fernández, José Ignacio Hidalgo, Juan Lanchares, J. M. Sánchez
    A methodology for reconfigurable hardware design based upon evolutionary computation. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:7, pp:363-371 [Journal]
  27. José Ignacio Hidalgo, Francisco Fernández de Vega, Juan Lanchares, Daniel Lombraña Gonzalez
    Is the island model fault tolerant? [Citation Graph (0, 0)][DBLP]
    GECCO, 2007, pp:1519- [Conf]
  28. José Ignacio Hidalgo, Juan Lanchares, Francisco Fernández de Vega, Daniel Lombraña Gonzalez
    Is the island model fault tolerant? [Citation Graph (0, 0)][DBLP]
    GECCO (Companion), 2007, pp:2737-2744 [Conf]
  29. Sonia López, Steve Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares
    Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2007, pp:136-150 [Conf]

  30. Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors. [Citation Graph (, )][DBLP]


  31. Design Flow of Dynamically-Allocated Data Types in Embedded Applications Based on Elitist Evolutionary Computation Optimization. [Citation Graph (, )][DBLP]


  32. Solving discrete deceptive problems with EMMRS. [Citation Graph (, )][DBLP]


  33. Analysis of multi-objective evolutionary algorithms to optimize dynamic data types in embedded systems. [Citation Graph (, )][DBLP]


  34. Mixed heuristic and mathematical programming using reference points for dynamic data types optimization in multimedia embedded systems. [Citation Graph (, )][DBLP]


  35. Improving reliability of embedded systems through dynamic memory manager optimization using grammatical evolution. [Citation Graph (, )][DBLP]


  36. Modelling Asynchronous Systems using Probability Distribution Functions. [Citation Graph (, )][DBLP]


  37. A Parallel Compact Genetic Algorithm for Multi-FPGA Partitioning. [Citation Graph (, )][DBLP]


  38. Optimization of dynamic data structures in multimedia embedded systems using evolutionary computation. [Citation Graph (, )][DBLP]


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