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David H. Albonesi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. David H. Albonesi, Israel Koren
    Improving the Memory Bandwidth of Highly-Integrated, Wide-Issue, Microprocessor-Based Systems. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1997, pp:126-135 [Conf]
  2. Steve Dropsho, Alper Buyuktosunoglu, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Greg Semeraro, Grigorios Magklis, Michael L. Scott
    Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2002, pp:141-0 [Conf]
  3. M. Wasiur Rashid, Edwin J. Tan, Michael C. Huang, David H. Albonesi
    Exploiting Coarse-Grain Verification Parallelism for Power-Efficient Fault Tolerance. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2005, pp:315-328 [Conf]
  4. YongKang Zhu, Grigorios Magklis, Michael L. Scott, Chen Ding, David H. Albonesi
    The Energy Impact of Aggressive Loop Fusion. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2004, pp:153-164 [Conf]
  5. Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott, Steven G. Dropsho, Sandhya Dwarkadas
    Hiding Synchronization Delays in a GALS Processor Microarchitecture. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:159-169 [Conf]
  6. Alper Buyuktosunoglu, David H. Albonesi, Stanley Schuster, David Brooks, Pradip Bose, Peter W. Cook
    A circuit level implementation of an adaptive issue queue for power-aware microprocessors. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:73-78 [Conf]
  7. Ali El-Moursy, David H. Albonesi
    Front-End Policies for Improved Issue Efficiency in SMT Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:31-0 [Conf]
  8. Lei Chen, Steve Dropsho, David H. Albonesi
    Dynamic Data Dependence Tracking and its Application to Branch Prediction. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:65-0 [Conf]
  9. Greg Semeraro, Grigorios Magklis, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Michael L. Scott
    Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:29-42 [Conf]
  10. David H. Albonesi
    An Architectural and Circuit-Level Approach to Improving the Energy Efficiency of Microprocessor Memory Structures. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:192-205 [Conf]
  11. Brian W. Curran, Mary Gifaldi, Jason Martin, Alper Buyuktosunoglu, Martin Margala, David H. Albonesi
    Low-Voltage 0, 25 µm CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:289-300 [Conf]
  12. David H. Albonesi, Israel Koren
    Tradeoffs in the Design of Single Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IFIP PACT, 1994, pp:25-34 [Conf]
  13. Ali El-Moursy, R. Garg, David H. Albonesi, Sandhya Dwarkadas
    Compatible phase co-scheduling on a CMP of multi-threaded processors. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  14. Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
    Dynamically allocating processor resources between nearby and distant ILP. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:26-37 [Conf]
  15. Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
    Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:275-286 [Conf]
  16. David H. Albonesi
    Dynamic IPC/Clock Rate Optimization. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:282-292 [Conf]
  17. Alper Buyuktosunoglu, Tejas Karkhanis, David H. Albonesi, Pradip Bose
    Energy Efficient Co-Adaptive Instruction Fetch and Issue. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:147-156 [Conf]
  18. Grigorios Magklis, Michael L. Scott, Greg Semeraro, David H. Albonesi, Steve Dropsho
    Profile-Based Dynamic Voltage and Frequency Scaling for a Multiple Clock Domain Microprocessor. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:14-25 [Conf]
  19. Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi
    Electrical and optical on-chip interconnects in scaled microprocessors. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2514-2517 [Conf]
  20. Alper Buyuktosunoglu, David H. Albonesi, Pradip Bose, Peter W. Cook, Stanley Schuster
    Tradeoffs in power-efficient issue queue design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:184-189 [Conf]
  21. Wael El-Essawy, David H. Albonesi, Balaram Sinharoy
    A microarchitectural-level step-power analysis tool. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:263-266 [Conf]
  22. YongKang Zhu, David H. Albonesi
    Synergistic temperature and energy management in GALS processor architectures. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:55-60 [Conf]
  23. David H. Albonesi
    Selective Cache Ways: On-Demand Cache Resource Allocation. [Citation Graph (0, 0)][DBLP]
    MICRO, 1999, pp:248-0 [Conf]
  24. Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas
    Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:245-257 [Conf]
  25. Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
    Reducing the complexity of the register file in dynamic superscalar processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:237-248 [Conf]
  26. Steve Dropsho, Volkan Kursun, David H. Albonesi, Sandhya Dwarkadas, Eby G. Friedman
    Managing static leakage energy in microprocessor functional units. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:321-332 [Conf]
  27. Steven G. Dropsho, Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott
    Dynamically Trading Frequency for Complexity in a GALS Microprocessor. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:157-168 [Conf]
  28. Greg Semeraro, David H. Albonesi, Steve Dropsho, Grigorios Magklis, Sandhya Dwarkadas, Michael L. Scott
    Dynamic frequency and voltage control for a multiple clock domain microarchitecture. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:356-367 [Conf]
  29. Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, José F. Martínez, Alyssa B. Apsel, Matthew A. Watkins, David H. Albonesi
    Leveraging Optical Technology in Future Bus-based Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:492-503 [Conf]
  30. Pradip Bose, David Brooks, Alper Buyuktosunoglu, Peter W. Cook, K. Das, Philip G. Emma, Michael Gschwind, Hans M. Jacobson, Tejas Karkhanis, Prabhakar Kudva, Stanley Schuster, James E. Smith, Viji Srinivasan, Victor V. Zyuban, David H. Albonesi, Sandhya Dwarkadas
    Early-Stage Definition of LPX: A Low Power Issue-Execute Processor. [Citation Graph (0, 0)][DBLP]
    PACS, 2002, pp:1-17 [Conf]
  31. Alper Buyuktosunoglu, Stanley Schuster, David Brooks, Pradip Bose, Peter W. Cook, David H. Albonesi
    An Adaptive Issue Queue for Reduced Power at High Performance. [Citation Graph (0, 0)][DBLP]
    PACS, 2000, pp:25-39 [Conf]
  32. Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi
    Predictions of CMOS compatible on-chip optical interconnect. [Citation Graph (0, 0)][DBLP]
    SLIP, 2005, pp:13-20 [Conf]
  33. David H. Albonesi, Rajeev Balasubramonian, Steve Dropsho, Sandhya Dwarkadas, Eby G. Friedman, Michael C. Huang, Volkan Kursun, Grigorios Magklis, Michael L. Scott, Greg Semeraro, Pradip Bose, Alper Buyuktosunoglu, Peter W. Cook, Stanley Schuster
    Dynamically Tuning Processor Resources with Adaptive Processing. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:12, pp:49-58 [Journal]
  34. Bingxiong Xu, David H. Albonesi
    Runtime Reconfiguration Techniques for Efficient General-Purpose Computation. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:1, pp:42-52 [Journal]
  35. Wanli Liu, David H. Albonesi, John Gostomski, Lloyd Palum, Dave Hinterberger, Rick Wanzenried, Mark Indovina
    An Evaluation of a Configurable Vliw Microarchitecture for Embedded Dsp Applications. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2004, v:13, n:6, pp:1321-1346 [Journal]
  36. David H. Albonesi
    Selective Cache Ways: On-Demand Cache Resource Allocation. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2000, v:2, n:, pp:- [Journal]
  37. Pradip Bose, David H. Albonesi, Diana Marculescu
    Guest Editors' Introduction: Power and Complexity Aware Design. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:5, pp:8-11 [Journal]
  38. David H. Albonesi
    Guest Editor's Introduction: Micro's Top Picks from Microarchitecture Conferences. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:6, pp:8-9 [Journal]
  39. Grigorios Magklis, Greg Semeraro, David H. Albonesi, Steve Dropsho, Sandhya Dwarkadas, Michael L. Scott
    Dynamic Frequency and Voltage Scaling for a Multiple-Clock-Domain Microprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:6, pp:62-68 [Journal]
  40. M. Wasiur Rashid, Edwin J. Tan, Michael C. Huang, David H. Albonesi
    Power-Efficient Error Tolerance in Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:6, pp:60-70 [Journal]
  41. Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas
    A Dynamically Tunable Memory Hierarchy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:10, pp:1243-1258 [Journal]
  42. Sonia López, Steve Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares
    Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2007, pp:136-150 [Conf]
  43. YongKang Zhu, David H. Albonesi
    Localized microarchitecture-level voltage management. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  44. Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, David H. Albonesi, Philippe M. Fauchet, Eby G. Friedman
    Predictions of CMOS compatible on-chip optical interconnect. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:4, pp:434-446 [Journal]
  45. David H. Albonesi
    Mixing It Up. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:4, pp:3-4 [Journal]
  46. David H. Albonesi
    More Hot Stuff. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:3, pp:4-5 [Journal]
  47. David H. Albonesi
    Editor in Chief's Message: Truly "hot" chips - Do we still care? [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:2, pp:4-5 [Journal]
  48. David H. Albonesi
    Standing on Solid Ground. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:1, pp:5-6 [Journal]
  49. Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, José F. Martínez, Alyssa B. Apsel, Matthew A. Watkins, David H. Albonesi
    On-Chip Optical Technology in Future Bus-Based Multicore Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:1, pp:56-66 [Journal]

  50. Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors. [Citation Graph (, )][DBLP]


  51. Scheduling algorithms for unpredictably heterogeneous CMP architectures. [Citation Graph (, )][DBLP]


  52. Shared reconfigurable architectures for CMPS. [Citation Graph (, )][DBLP]


  53. Phastlane: a rapid transit optical routing network. [Citation Graph (, )][DBLP]


  54. A High Performance, Energy Efficient GALS ProcessorMicroarchitecture with Reduced Implementation Complexity. [Citation Graph (, )][DBLP]


  55. Partitioning Multi-Threaded Processors with a Large Number of Threads. [Citation Graph (, )][DBLP]


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