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Chih-Wea Wang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin
    Test Scheduling and Test Access Architecture Optimization for System-on-Chip. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:411-0 [Conf]
  2. Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin
    Test Scheduling of BISTed Memory Cores for SOC. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:356-0 [Conf]
  3. Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang, Shyh-Horng Lin, Hsin-Po Wang
    A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:103-0 [Conf]
  4. Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin
    A built-in self-test and self-diagnosis scheme for embedded SRAM. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:45-50 [Conf]
  5. Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Chih-Wea Wang, Cheng-Wen Wu
    Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:301-306 [Conf]
  6. Yu-Tsao Hsing, Chih-Wea Wang, Ching-Wei Wu, Chih-Tsun Huang, Cheng-Wen Wu
    Failure Factor Based Yield Enhancement for SRAM Designs. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:20-28 [Conf]
  7. Kuo-Liang Cheng, Chih-Wea Wang, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu
    FAME: A Fault-Pattern Based Memory Failure Analysis Framework. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:595-598 [Conf]
  8. Chi-Feng Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-Liang Cheng, Cheng-Wen Wu
    Error Catch and Analysis for Semiconductor Memories Using March Tests. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:468-471 [Conf]
  9. Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Chih-Yen Lo, Li-Ming Denq, Chih-Tsun Huang, Shin-Wei Hung, Jye-Yuan Lee
    An SOC Test Integration Platform and Its Industrial Realization. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1213-1222 [Conf]
  10. Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu, Frank Huang, Hong-Tzer Yang
    Fault Pattern Oriented Defect Diagnosis for Memories. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:29-38 [Conf]
  11. Kuo-Liang Cheng, Jen-Chieh Yeh, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu
    RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:281-288 [Conf]
  12. Chih-Wea Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
    Test and Diagnosis of Word-Oriented Multiport Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:248-253 [Conf]
  13. Chih-Yen Lo, Chen-Hsing Wang, Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Shin-Moe Wang, Cheng-Wen Wu
    STEAC: A Platform for Automatic SOC Test Integration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:541-545 [Journal]

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