Conferences in DBLP
Jon Fields Keynote Address. [Citation Graph (0, 0)][DBLP ] Conf ] Philippe Magarshack Invited Keynote: Building Yield into Systems-on-Chips for Nanometer Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Samitha Samaranayake , Emil Gizdarski , Nodari Sitchinava , Frederic Neuveux , Rohit Kapur , Thomas W. Williams A Reconfigurable Shared Scan-in Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Manish Sharma , Janak H. Patel , Jeff Rearick Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Magdy S. Abadir , Juhong Zhu Transition Test Generation using Replicate-and-Reduce Transform for Scan-based Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Sagar S. Sabade , D. M. H. Walker Use of Multiple IDDQ Test Metrics for Outlier Identification. [Citation Graph (0, 0)][DBLP ] Conf ] Brady Benware , Robert Madge , Cam Lu , W. Robert Daasch Effectiveness Comparisons of Outlier Screening Methods for Frequency Dependent Defects on Complex ASICs. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas J. Vogels Effectiveness of I-V Testing in Comparison to IDDq Tests. [Citation Graph (0, 0)][DBLP ] Conf ] Grzegorz Mrugalski , Janusz Rajski , Jerzy Tyszer High Speed Ring Generators and Compactors of Test Data. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmad A. Al-Yamani , Edward J. McCluskey Built-In Reseeding for Serial Bist. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmad A. Al-Yamani , Subhasish Mitra , Edward J. McCluskey Bist Reseeding with very few Seeds. [Citation Graph (0, 0)][DBLP ] Conf ] Marcelo Negreiros , Luigi Carro , Altamiro Amadeu Susin Ultra Low Cost Analog BIST Using Spectral Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Hak-soo Yu , Sungbae Hwang , Jacob A. Abraham DSP-Based Statistical Self Test of On-Chip Converters. [Citation Graph (0, 0)][DBLP ] Conf ] Soumendu Bhattacharya , Abhijit Chatterjee High Coverage Analog Wafer-Probe Test Design and Co-optimization with Assembled-Package Test to Minimize Overall Test Cost. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Wohl , Leendert M. Huisman Analysis and Design of Optimal Combinational Compactors. [Citation Graph (0, 0)][DBLP ] Conf ] Janak H. Patel , Steven S. Lumetta , Sudhakar M. Reddy Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns. [Citation Graph (0, 0)][DBLP ] Conf ] Ismet Bayraktaroglu , Alex Orailoglu Decompression Hardware Determination for Test Volume and Time Reduction through Unified Test Pattern Compaction and Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Kartik Mohanram , Nur A. Touba Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential Buses. [Citation Graph (0, 0)][DBLP ] Conf ] Érika F. Cota , Márcio Eduardo Kreutz , Cesar Albenes Zeferino , Luigi Carro , Marcelo Lubaszewski , Altamiro Amadeu Susin The Impact of NoC Reuse on the Testing of Core-based Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Mehdi Baradaran Tahoori , Subhasish Mitra Automatic Configuration Generation for FPGA Interconnect Testing. [Citation Graph (0, 0)][DBLP ] Conf ] José Pineda de Gyvez , Rosa Rodríguez-Montañés Threshold Voltage Mismatch (DeltaVT) Fault Modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Yi-Shing Chang , Sandeep K. Gupta , Melvin A. Breuer Test Generation for Maximizing Ground Bounce Considering Circuit Delay. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammad H. Tehranipour , Nisar Ahmed , Mehrdad Nourani Testing SoC Interconnects for Signal Integrity Using Boundary Scan. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Aiman H. El-Maleh , Khaled Al-Utaibi An Efficient Test Relaxation Technique for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Nabil M. Abdulrazzaq , Sandeep K. Gupta Path-Delay Fault Simulation for Circuits with Large Numbers of Paths for Very Large Test Sets. [Citation Graph (0, 0)][DBLP ] Conf ] Chauchin Su , Chih-Hu Wang , Wei-Juo Wang , I. S. Tseng 1149.4 Based On-Line Quiescent State Monitoring Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Mani Soma , Welela Haileselassie , Jessica Sherrid Measurement of Phase and Frequency Variations in Radio-Frequency Signal. [Citation Graph (0, 0)][DBLP ] Conf ] Haralampos-G. D. Stratigopoulos , Yiorgos Makris An Analog Checker with Dynamically Adjustable Error Threshold for Fully Differential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Lei Li , Krishnendu Chakrabarty Test Data Compression Using Dictionaries with Fixed-Length Indices. [Citation Graph (0, 0)][DBLP ] Conf ] Kedarnath J. Balakrishnan , Nur A. Touba Deterministic Test Vector Decompression in Software Using Linear Operations. [Citation Graph (0, 0)][DBLP ] Conf ] Erik H. Volkerink , Subhasish Mitra Efficient Seed Utilization for Reseeding based Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Said Hamdioui , A. J. van de Goor , Mike Rodgers Detecting Intra-Word Faults in Word-Oriented Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Wea Wang , Kuo-Liang Cheng , Chih-Tsun Huang , Cheng-Wen Wu Test and Diagnosis of Word-Oriented Multiport Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Sultan M. Al-Harbi , Sandeep K. Gupta Generating Complete and Optimal March Tests for Linked Faults in Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoding Chen , Michael S. Hsiao Energy-Efficient Logic BIST Based on State Correlation Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Dan Zhao , Shambhu J. Upadhyaya Power Constrained Test Scheduling with Dynamically Varied TAM. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoyun Sun , Larry L. Kinney , Bapiraju Vinnakota Development of Energy Consumption Ratio Test. [Citation Graph (0, 0)][DBLP ] Conf ] Tomokazu Yoneda , Hideo Fujiwara Design for Consecutive Transparency of Cores in System-on-a-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Mohsen Nahvi , André Ivanov An Embedded Autonomous Scan-Based Results Analyzer (EARA) for SoC Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Vikram Iyengar , Krishnendu Chakrabarty , Mark D. Krasniewski , Gopind N. Kumar Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs. [Citation Graph (0, 0)][DBLP ] Conf ] Kaushik Roy , T. M. Mak , Kwang-Ting Cheng Embedded Tutorial: Test Consideration for Nanometer Scale CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Erik Larsson , Hideo Fujiwara Test Resource Partitioning and Optimization for SOC Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Zou , Sudhakar M. Reddy , Irith Pomeranz , Yu Huang SOC Test Scheduling Using Simulated Annealing. [Citation Graph (0, 0)][DBLP ] Conf ] Man Wah Chiang , Zeljko Zilic Layered Approach to Designing System Test Interfaces. [Citation Graph (0, 0)][DBLP ] Conf ] Angela Krstic , Li-C. Wang , Kwang-Ting Cheng , Jing-Jia Liou Diagnosis of Delay Defects Using Statistical Timing Models. [Citation Graph (0, 0)][DBLP ] Conf ] Ananta K. Majhi , Guido Gronthoud , Camelia Hora , Maurice Lousberg , Pop Valer , Stefan Eichenberger Improving Diagnostic Resolution of Delay Faults using Path Delay Fault Model. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoming Yu , Enamul Amyeen , Srikanth Venkataraman , Ruifeng Guo , Irith Pomeranz Concurrent Execution of Diagnostic Fault Simulation and Equivalence Identification During Diagnostic Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Takahisa Hiraide , Kwame Osei Boateng , Hideaki Konishi , Koichi Itaya , Michiaki Emori , Hitoshi Yamanaka , Takashi Mochiyama BIST-Aided Scan Test - A New Method for Test Cost Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitri Kagaris Built-In TPG with Designed Phaseshifts. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy , Yervant Zorian A Test Interface for Built-In Test of Non-Isolated Scanned Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Zhuo Li , Xiang Lu , Wangqi Qiu , Weiping Shi , D. M. H. Walker A Circuit Level Fault Model for Resistive Opens and Bridges. [Citation Graph (0, 0)][DBLP ] Conf ] Shahdad Irajpour , Shahin Nazarian , Lei Wang , Sandeep K. Gupta , Melvin A. Breuer Analyzing Crosstalk in the Presence of Weak Bridge Defects. [Citation Graph (0, 0)][DBLP ] Conf ] Manan Syal , Michael S. Hsiao , Kiran B. Doreswamy , Sreejit Chakravarty Efficient Implication - Based Untestable Bridge Fault Identifier. [Citation Graph (0, 0)][DBLP ] Conf ] Hans G. Kerkhoff , Mustafa Acar Testable Design and Testing of Micro-Electro-Fluidic Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Ketan N. Patel , John P. Hayes , Igor L. Markov Fault Testing for Reversible Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jing-ling Yang , Oliver Chiu-sing Choy , Cheong-fat Chan , Kong-Pong Pun Design for Self-Checking and Self-Timed Datapath. [Citation Graph (0, 0)][DBLP ] Conf ] 