The SCEAS System
Navigation Menu

Search the dblp DataBase


Claude Thibeault: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. J. Crépeau, Claude Thibeault, Yvon Savaria
    Some Results on Yield and Local Design Rule Relaxation. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:144-151 [Conf]
  2. Yves Gagnon, Yvon Savaria, Michel Meunier, Claude Thibeault
    Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:157-165 [Conf]
  3. Y. Hariri, Claude Thibeault
    3DSDM: A 3 Data-Source Diagnostic Method. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:117-123 [Conf]
  4. Michel Kafrouni, Claude Thibeault, Yvon Savaria
    A Cost Model for VLSI / MCM Systems. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:148-156 [Conf]
  5. Bing Qiu, Yvon Savaria, Meng Lu, Chunyan Wang, Claude Thibeault
    Yield Modeling of a WSI Telecom Router Architecture. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:314-324 [Conf]
  6. Claude Thibeault
    Using Fourier Analysis to Enhance IC Testability. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:280-298 [Conf]
  7. Claude Thibeault
    Increasing Current Testing Resolution. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:126-134 [Conf]
  8. Claude Thibeault, Luc Boisvert
    On the Current Behavior of Faulty and Fault-Free ICs and the Impact on Diagnosis. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:202-210 [Conf]
  9. Claude Thibeault
    Improving Delta-I_DDQ-based test methods. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:207-216 [Conf]
  10. Claude Thibeault
    An histogram based procedure for current testing of active defects. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:714-723 [Conf]
  11. Claude Thibeault, Luc Boisvert
    Diagnosis method based on /spl Delta/Iddq probabilistic signatures: experimental results. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:1019-1026 [Conf]
  12. Ginette Monté, Bernard Antaki, Serge Patenaude, Yvon Savaria, Claude Thibeault, Pieter M. Trouborst
    Tools for the Characterization of Bipolar CML Testability. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:388-395 [Conf]
  13. Claude Thibeault
    Efficient Diagnosis of Single/Double Bridging Faults with Delta Iddq Probabilistic Signatures and Viterbi Algorithm. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:431-438 [Conf]
  14. Claude Thibeault
    Speeding-Up IDDQ Measurements. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:295-301 [Conf]
  15. Claude Thibeault
    On New Current Signatures and Adaptive Test Technique Combination. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:59-64 [Conf]
  16. Claude Thibeault
    Detection and location of faults and defects using digital signal processing. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:262-269 [Conf]
  17. Claude Thibeault
    A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:80-87 [Conf]
  18. Claude Thibeault
    On the Comparison of IDDQ and IDDQ Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:143-151 [Conf]
  19. Claude Thibeault
    On a New Outlier Rejection Technique. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:97-103 [Conf]
  20. Yervant Zorian, Tom Anderson, Yvon Savaria, Claude Thibeault, André Ivanov
    Panel Summaries. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:3, pp:6-112 [Journal]
  21. Claude Thibeault
    On the Adaptation of Viterbi Algorithm for Diagnosis of Multiple Bridging Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:6, pp:575-587 [Journal]
  22. Claude Thibeault, Guy Bégin
    A Scan-Based Configurable, Programmable and Scalable Architecture for Sliding Window-Based Operations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:6, pp:615-627 [Journal]
  23. Claude Thibeault, Yvon Savaria, Jean-Louis Houle
    A Fast Method to Evaluate the Optimum Number of Spares in Defect-Tolerant Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:6, pp:687-698 [Journal]
  24. Claude Thibeault, Yvon Savaria, Jean-Louis Houle
    Equivalence Proofs of Some Yield Modeling Methods for Defect-Tolerant Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:5, pp:724-728 [Journal]

Search in 0.002secs, Finished in 0.003secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002