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Publications of Author

1. Abu S. M. Hassan, Vinod K. Agarwal, Janusz Rajski, Benoit Nadeau-Dostie
   Testing of Glue Logic Interconnects Using Boundary Scan Architecture. [Citation Graph (0, 0)][DBLP]
   ITC, 1989, pp:700-711 [Conf]
   
2. Benoit Nadeau-Dostie, Dwayne Burek, Abu S. M. Hassan
   ScanBIST: A Multi-frequency Scan-based BIST Method. [Citation Graph (0, 0)][DBLP]
   ITC, 1992, pp:506-513 [Conf]
   
3. Benoit Nadeau-Dostie, Jean-Francois Cote, Harry Hulvershorn, Stephen Pateras
   An embedded technique for at-speed interconnect testing. [Citation Graph (0, 0)][DBLP]
   ITC, 1999, pp:431-438 [Conf]
   
4. Benoit Nadeau-Dostie, Harry Hulvershorn, Saman Adham
   A New Hardware Fault Insertion Scheme for System Diagnostics Verification. [Citation Graph (0, 0)][DBLP]
   ITC, 1995, pp:994-1002 [Conf]
   
5. Stephen K. Sunter, Benoit Nadeau-Dostie
   Complete, Contactless I/O Testing - Reaching the Boundary in Minimizing Digital IC Testing Cost. [Citation Graph (0, 0)][DBLP]
   ITC, 2002, pp:446-455 [Conf]
   
6. Saman Adham, Benoit Nadeau-Dostie
   A BIST Algorithm for Bit/Group Write Enable Faults in SRAMs. [Citation Graph (0, 0)][DBLP]
   MTDT, 2004, pp:98-101 [Conf]
   
7. Bernd Könemann, Ben Bennetts, Najmi T. Jarwala, Benoit Nadeau-Dostie
   Built-In Self-Test: Assuring System Integrity. [Citation Graph (0, 0)][DBLP]
   IEEE Computer, 1996, v:29, n:11, pp:39-45 [Journal]
   
8. Benoit Nadeau-Dostie, Dwayne Burek, Abu S. M. Hassan
   ScanBist: A Multifrequency Scan-Based BIST Method. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1994, v:11, n:1, pp:7-17 [Journal]
   
9. Benoit Nadeau-Dostie, Allan Silburt, Vinod K. Agarwal
   Serial Interfacing for Embedded-Memory Testing. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1990, v:7, n:2, pp:52-63 [Journal]
   
10. Samir Boubezari, Eduard Cerny, Bozena Kaminska, Benoit Nadeau-Dostie
    Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1327-1340 [Journal]
    
11. Abu S. M. Hassan, Vinod K. Agarwal, Benoit Nadeau-Dostie, Janusz Rajski
    BIST of PCB interconnects using boundary-scan architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:10, pp:1278-1288 [Journal]
    
12. 
    Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points. [Citation Graph (, )][DBLP]
    
    
13. 
    Improved Core Isolation and Access for Hierarchical Embedded Test. [Citation Graph (, )][DBLP]