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Publications of Author

1. I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz, D. F. Wong
   Integrated power supply planning and floorplanning. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2001, pp:589-594 [Conf]
   
2. Li-Da Huang, Hung-Ming Chen, D. F. Wong
   Global Wire Bus Configuration with Minimum Delay Uncertainty. [Citation Graph (0, 0)][DBLP]
   DATE, 2003, pp:10050-10055 [Conf]
   
3. Bo-Fu Liu, Hung-Ming Chen, Jian-Hung Chen, Shiow-Fen Hwang, Shinn-Ying Ho
   MeSwarm: memetic particle swarm optimization. [Citation Graph (0, 0)][DBLP]
   GECCO, 2005, pp:267-268 [Conf]
   
4. Hung-Ming Chen, D. F. Wong, Wai-Kei Mak, Hannah Honghua Yang
   Faster and more accurate wiring evaluation in interconnect-centric floorplanning. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2001, pp:62-67 [Conf]
   
5. Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani
   Integrated floorplanning and interconnect planning. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1999, pp:354-357 [Conf]
   
6. Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzhou Shao, Li-Da Huang
   I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. [Citation Graph (0, 0)][DBLP]
   ICCD, 2004, pp:562-567 [Conf]
   
7. Li-Chung Hsu, Hung-Ming Chen
   On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design. [Citation Graph (0, 0)][DBLP]
   ISQED, 2006, pp:451-456 [Conf]
   
8. Muzhou Shao, Youxin Gao, Li-Pen Yuan, Hung-Ming Chen, Martin D. F. Wong
   Current Calculation on VLSI Signal Interconnects. [Citation Graph (0, 0)][DBLP]
   ISQED, 2005, pp:580-585 [Conf]
   
9. Shinn-Ying Ho, Chih-Hung Hsieh, Kuan-Wei Chen, Hui-Ling Huang, Hung-Ming Chen, Shinn-Jang Ho
   Scoring Method for Tumor Prediction from Microarray Data Using an Evolutionary Fuzzy Classifier. [Citation Graph (0, 0)][DBLP]
   PAKDD, 2006, pp:520-529 [Conf]
   
10. Jian-Hung Chen, Hung-Ming Chen, Shinn-Ying Ho
    Design of Nearest Neighbor Classifiers Using an Intelligent Multi-objective Evolutionary Algorithm. [Citation Graph (0, 0)][DBLP]
    PRICAI, 2004, pp:262-271 [Conf]
    
11. Jian-Hung Chen, Hung-Ming Chen, Shinn-Ying Ho
    Design of nearest neighbor classifiers: multi-objective approach. [Citation Graph (0, 0)][DBLP]
    Int. J. Approx. Reasoning, 2005, v:40, n:1-2, pp:3-22 [Journal]
    
12. Hung-Ming Chen, Li-Da Huang, I-Min Liu, Martin D. F. Wong
    Simultaneous power supply planning and noise avoidance in floorplan design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:578-587 [Journal]
    
13. Hung-Ming Chen, I-Min Liu, Martin D. F. Wong
    I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2552-2556 [Journal]
    
14. Shinn-Ying Ho, Hung-Ming Chen, Shinn-Jang Ho, Tai-Kang Chen
    Design of accurate classifiers with a compact fuzzy-rule base using an evolutionary scatter partition of feature space. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Systems, Man, and Cybernetics, Part B, 2004, v:34, n:2, pp:1031-1044 [Journal]
    
15. Po-Hung Chen, Hung-Ming Chen, Kuo-Jui Hung, Wen-Hsien Fang, Mon-Chau Shie, Feipei Lai
    Markov model fuzzy-reasoning based algorithm for fast block motion estimation. [Citation Graph (0, 0)][DBLP]
    J. Visual Communication and Image Representation, 2006, v:17, n:1, pp:131-142 [Journal]
    
16. Bo-Fu Liu, Hung-Ming Chen, Hui-Ling Huang, Shiow-Fen Hwang, Shinn-Ying Ho
    Flexible protein-ligand docking using particle swarm optimization. [Citation Graph (0, 0)][DBLP]
    Congress on Evolutionary Computation, 2005, pp:251-258 [Conf]
    
17. Shinri-Ying Ho, Chong-Cheng Lee, Hung-Ming Chen, Hui-Ling Huang
    Efficient gene selection for classification of microarray data. [Citation Graph (0, 0)][DBLP]
    Congress on Evolutionary Computation, 2005, pp:1753-1760 [Conf]
    
18. 
    On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design. [Citation Graph (, )][DBLP]
    
    
19. 
    Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign. [Citation Graph (, )][DBLP]
    
    
20. 
    Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design. [Citation Graph (, )][DBLP]
    
    
21. 
    Efficient and optimal post-layout double-cut via insertion by network relaxation and min-cost maximum flow. [Citation Graph (, )][DBLP]
    
    
22. 
    A stochastic-based efficient critical area extractor on OpenAccess platform. [Citation Graph (, )][DBLP]
    
    
23. 
    A selective pattern-compression scheme for power and test-data reduction. [Citation Graph (, )][DBLP]
    
    
24. 
    Blockage and voltage island-aware dual-vdd buffered tree construction under fixed buffer locations. [Citation Graph (, )][DBLP]
    
    
25. 
    An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign. [Citation Graph (, )][DBLP]
    
    
26. 
    Buffer/flip-flop block planning for power-integrity-driven floorplanning. [Citation Graph (, )][DBLP]
    
    
27. 
    A novel two-dimensional scan-control scheme for test-cost reduction. [Citation Graph (, )][DBLP]