Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2006, volume: 25, number: 11

1. Chai Wang, Bing Li, HoonSang Jin, Gary D. Hachtel, Fabio Somenzi
   Improving Ariadne's Bundle by Following Multiple Threads in Abstraction Refinement. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2297-2316 [Journal]
   
2. Pallav Gupta, Abhinav Agrawal, Niraj K. Jha
   An Algorithm for Synthesis of Reversible Logic Circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2317-2330 [Journal]
   
3. Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic
   Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2331-2340 [Journal]
   
4. C.-T. Hsieh, J.-C. Lin, S.-C. Chang
   Vectorless Estimation of Maximum Instantaneous Current for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2341-2352 [Journal]
   
5. Nikolay Rubanov
   A High-Performance Subcircuit Recognition Method Based on the Nonlinear Graph Optimization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2353-2363 [Journal]
   
6. Soheil Ghiasi, Elaheh Bozorgzadeh, Po-Kuan Huang, Roozbeh Jafari, Majid Sarrafzadeh
   A Unified Theory of Timing Budget Management. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2364-2375 [Journal]
   
7. Jochen A. G. Jess, K. Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah
   Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2376-2392 [Journal]
   
8. W.-K. Mak, C.-L. Lai
   On Constrained Pin-Mapping for FPGA-PCB Codesign. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2393-2401 [Journal]
   
9. Hang Li, Jeffrey Fan, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong
   Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2402-2412 [Journal]
   
10. Paolo Maffezzoni, L. Codecasa, Dario D'Amore
    Event-Driven Time-Domain Simulation of Closed-Loop Switched Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2413-2426 [Journal]
    
11. Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy
    Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2427-2436 [Journal]
    
12. Lizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubner, Charlie Chung-Ping Chen
    Correlation-Preserved Statistical Timing With a Quadratic Form of Gaussian Variables. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2437-2449 [Journal]
    
13. Ronald D. Blanton, Kumar N. Dwarakanath, Rao Desineni
    Defect Modeling Using Fault Tuples. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2450-2464 [Journal]
    
14. Érika F. Cota, Chunsheng Liu
    Constraint-Driven Test Scheduling for NoC-Based Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2465-2478 [Journal]
    
15. Petros Oikonomakos, Mark Zwolinski
    An Integrated High-Level On-Line Test Synthesis Tool. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2479-2491 [Journal]
    
16. Irith Pomeranz, Sudhakar M. Reddy
    Improved n-Detection Test Sequences Under Transparent Scan. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2492-2501 [Journal]
    
17. Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu Chakrabarty
    Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2502-2512 [Journal]
    
18. Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee, Jwu E. Chen
    IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2513-2525 [Journal]
    
19. Liang Zhang, Indradeep Ghosh, Michael S. Hsiao
    A Framework for Automatic Design Validation of RTL Circuits Using ATPG and Observability-Enhanced Tag Coverage. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2526-2538 [Journal]
    
20. Milos Hrkic, John Lillis, Giancarlo Beraudo
    An Approach to Placement-Coupled Logic Replication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2539-2551 [Journal]
    
21. Hung-Ming Chen, I-Min Liu, Martin D. F. Wong
    I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2552-2556 [Journal]
    
22. Aiman H. El-Maleh, S. Saqib Khursheed, Sadiq M. Sait
    Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse-Order Restoration and Test Relaxation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2556-2564 [Journal]
    
23. Feng Gao, John P. Hayes
    Exact and Heuristic Approaches to Input Vector Control for Leakage Power Reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2564-2571 [Journal]
    
24. Yutao Hu, Kartikeya Mayaram
    Comparison of Algorithms for Frequency Domain Coupled Device and Circuit Simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2571-2578 [Journal]
    
25. Dimitrios Kagaris, P. Karpodinis, Dimitris Nikolos
    On Obtaining Maximum-Length Sequences for Accumulator-Based Serial TPG. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2578-2586 [Journal]
    
26. N.-C. Lai, S.-J. Wang, Y.-H. Fu
    Low-Power BIST With a Smoother and Scan-Chain Reorder Under Optimal Cluster Size. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2586-2594 [Journal]
    
27. Fang Liu, Sule Ozev, Martin A. Brooke
    Identifying the Source of BW Failures in High-Frequency Linear Analog Circuits Based on S-Parameter Measurements. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2594-2605 [Journal]
    
28. P. Min, H. Yi, J. Song, S. Baeg, S. Park
    Efficient Interconnect Test Patterns for Crosstalk and Static Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2605-2608 [Journal]