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Conferences in DBLP

Symposium on Asynchronous Circuits and Systems (async)
2003 (conf/async/2003)

  1. Robert B. Reese, Mitchell A. Thornton, Cherrice Traver
    A Coarse-Grain Phased Logic CPU. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:2-13 [Conf]
  2. Alain J. Martin, Mika Nyström, Karl Papadantonakis, Paul I. Pénzes, Piyush Prakash, Catherine G. Wong, Jonathan Chang, Kevin S. Ko, Benjamin Lee, Elaine Ou, James Pugh, Eino-Ville Talvala, James T. Tong, Ahmet Tura
    The Lutonium: A Sub-Nanojoule Asynchronous 8051 Microcontroller. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:14-23 [Conf]
  3. Clinton Kelly IV, Virantha N. Ekanayake, Rajit Manohar
    SNAP: A Sensor-Network Asynchronous Processor. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:24-35 [Conf]
  4. William S. Coates, Robert J. Drost
    Congestion and Starvation Detection in Ripple FIFOs. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:36-45 [Conf]
  5. Aristides Efthymiou, Jim D. Garside
    Adaptive Pipeline Structures fo Speculation Control. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:46-55 [Conf]
  6. Kenneth S. Stevens
    Energy and Performance Models for Clocked and Asynchronous Communication. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:56-67 [Conf]
  7. Yaron Semiat, Ran Ginosar
    Timing Measurements of Synchronization Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:68-77 [Conf]
  8. Ajanta Chakraborty, Mark R. Greenstreet
    Efficient Self-Timed Interfaces for Crossing Clock Domains. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:78-88 [Conf]
  9. Ran Ginosar
    Fourteen Ways to Fool Your Synchronizer. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:89-97 [Conf]
  10. Nikolai Starodoubtsev, Sergei Bystrov, Alexandre Yakovlev
    Monotonic Circuits with Complete Acknowledgement. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:98-108 [Conf]
  11. Steven M. Nowick, Charles W. O'Donnell
    On the Existence of Hazard-Free Multi-Level Logic. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:109-120 [Conf]
  12. Mark B. Josephs
    An Analysis of Determinacy Using a Trace-Theoretic Model of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:121-131 [Conf]
  13. W. J. Bainbridge, W. B. Toms, David A. Edwards, Stephen B. Furber
    Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:132-140 [Conf]
  14. Thomas Villiger, Hubert Kaeslin, Frank K. Gürkaynak, Stephan Oetiker, Wolfgang Fichtner
    Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:141-150 [Conf]
  15. John Teifel, Rajit Manohar
    A High-Speed Clockless Serial Link Transceiver. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:151-163 [Conf]
  16. Alexandre V. Bystrov, Danil Sokolov, Alexandre Yakovlev
    Low-Latency Contro Structures with Slack. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:164-173 [Conf]
  17. Virantha N. Ekanayake, Rajit Manohar
    Asynchronous DRAM Design and Synthesis. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:174-183 [Conf]
  18. Hiroshi Saito, Euiseok Kim, Nattha Sretasereekul, Masashi Imai, Hiroshi Nakamura, Takashi Nanya
    Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:184-195 [Conf]
  19. Emmanuel Allier, Gilles Sicard, Laurent Fesquet, Marc Renaudin
    A New Class of Asynchronous A/D Converters Based on Time Quantization. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:196-205 [Conf]
  20. Z. C. Yu, Stephen B. Furber, Luis A. Plana
    An Investigation into the Security of Self-Timed Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:206-215 [Conf]
  21. Yee William Li, George Patounakis, Anup Jose, Kenneth L. Shepard, Steven M. Nowick
    Asynchronous Datapath with Software-Controlled On-Chip Adaptive Voltage Scaling for Multirate Signal Processing Application. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:216-226 [Conf]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002