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Tien-Fu Chen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Tien-Fu Chen, Jean-Loup Baer
    Reducing Memory Latency via Non-blocking and Prefetching Caches. [Citation Graph (2, 0)][DBLP]
    ASPLOS, 1992, pp:51-61 [Conf]
  2. Tien-Fu Chen
    Efficient trace-sampling simulation techniques for cache performance analysis. [Citation Graph (0, 0)][DBLP]
    Annual Simulation Symposium, 1996, pp:54-0 [Conf]
  3. Jean-Loup Baer, Tien-Fu Chen
    An Evaluation of Hardware and Software Data Prefetching. [Citation Graph (0, 0)][DBLP]
    Applications in Parallel and Distributed Computing, 1994, pp:257-266 [Conf]
  4. Jian-Liang Kuo, Tien-Fu Chen
    Dynamic voltage leveling scheduling for real-time embedded systems on low-power variable speed processors. [Citation Graph (0, 0)][DBLP]
    CASES, 2002, pp:147-155 [Conf]
  5. Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
    Crossroad System-on-Chip Communication Architecture for Low Power Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ESA, 2005, pp:151-157 [Conf]
  6. Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
    Fast Run-Time Power Monitoring Methodology for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ESA, 2006, pp:129-133 [Conf]
  7. Kuei-Chung Chang, Tien-Fu Chen, Wei-Yen Chuang
    System-Level Power-Aware Scheduling by Operation-based Prediction. [Citation Graph (0, 0)][DBLP]
    PSC, 2005, pp:154-160 [Conf]
  8. Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
    Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:143-148 [Conf]
  9. Tien-Fu Chen
    Supporting Highly-Speculative Execution via Adaptive Branch Trees. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:185-194 [Conf]
  10. Wann-Yun Shieh, Tien-Fu Chen, Chung-Ping Chung
    A Tree-Based inverted File for Fast Ranked-Document Retrieval. [Citation Graph (0, 0)][DBLP]
    IKE, 2003, pp:64-69 [Conf]
  11. Tien-Fu Chen, Jean-Loup Baer
    A Performance Study of Software and Hardware Data Prefetching Schemes. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:223-232 [Conf]
  12. Chih-Da Chien, Chien-Chang Lin, Jiun-In Guo, Tien-Fu Chen
    A power-aware IP core generator for the one-dimensional discrete Fourier transform. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2004, pp:637-640 [Conf]
  13. Tien-Fu Chen, Tsung-Ming Hsieh, Chun-Li Wei
    Unified bus encoding by stream reconstruction with variable strides. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:329-332 [Conf]
  14. Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Tien-Fu Chen
    A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:141-144 [Conf]
  15. Rei-Chin Ju, Jia-Wei Chen, Jiun-In Guo, Tien-Fu Chen
    A parameterized power-aware IP core generator for the 2-D 8×8 DCT/IDCT. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:769-772 [Conf]
  16. Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
    A low-power crossroad switch architecture and its core placement for network-on-chip. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:375-380 [Conf]
  17. Tien-Fu Chen
    An effective programmable prefetch engine for on-chip caches. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:237-242 [Conf]
  18. Chih-wen Hsueh, Tien-Fu Chen, Rong-Guey Chang, Shi-Wu Lo
    Development of Architecture and Software Technologies in High-Performance Low-Power SoC Design. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2005, pp:475-480 [Conf]
  19. Chi-Min Lin, Tien-Fu Chen
    Dynamic memory management for real-time embedded Java chips. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2000, pp:49-56 [Conf]
  20. Jean-Loup Baer, Tien-Fu Chen
    An effective on-chip preloading scheme to reduce data access penalty. [Citation Graph (0, 0)][DBLP]
    SC, 1991, pp:176-186 [Conf]
  21. Chung-Hung Lai, Tien-Fu Chen
    Compressing inverted files in scalable information systems by binary decision diagram encoding . [Citation Graph (0, 0)][DBLP]
    SC, 2001, pp:60- [Conf]
  22. Chia-Ming Hsu, Tien-Fu Chen
    Flexible Heterogeneous Multicore Architectures for Media Processing via Customized Long Instruction Words. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:270-275 [Conf]
  23. Hao-Ran Liu, Tien-Fu Chen
    A Scalable Locality-Aware Event Dispatching Mechanism for Network Servers. [Citation Graph (0, 0)][DBLP]
    WWW (Posters), 2003, pp:- [Conf]
  24. Hao-Ran Liu, Tien-Fu Chen
    Scalable locality-aware event dispatching mechanism for network servers. [Citation Graph (0, 0)][DBLP]
    IEE Proceedings - Software, 2004, v:151, n:3, pp:129-138 [Journal]
  25. Wann-Yun Shieh, Tien-Fu Chen, Jean Jyh-Jiun Shann, Chung-Ping Chung
    Inverted file compression through document identifier reassignment. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Manage., 2003, v:39, n:1, pp:117-131 [Journal]
  26. Tien-Fu Chen
    Techniques for The Efficient Analysis of Cache Performance. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1996, v:12, n:4, pp:483-509 [Journal]
  27. Hung-Cheng Wu, Tien-Fu Chen, Hung-Yu Li, Jinn-Shyan Wang
    Energy Efficient Caching-on-Cache Architectures for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2003, v:19, n:5, pp:809-825 [Journal]
  28. Yung-Cheng Ma, Tien-Fu Chen, Chung-Ping Chung
    Branch-and-bound task allocation with task clustering-based pruning. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2004, v:64, n:11, pp:1223-1240 [Journal]
  29. Yung-Cheng Ma, Tien-Fu Chen, Chung-Ping Chung
    Posting file partitioning and parallel information retrieval. [Citation Graph (0, 0)][DBLP]
    Journal of Systems and Software, 2002, v:63, n:2, pp:113-127 [Journal]
  30. Yung-Cheng Ma, Jih-Ching Chiu, Tien-Fu Chen, Chung-Ping Chung
    Variable-size data item placement for load and storage balancing. [Citation Graph (0, 0)][DBLP]
    Journal of Systems and Software, 2003, v:66, n:2, pp:157-166 [Journal]
  31. Tien-Fu Chen, Jean-Loup Baer
    Effective Hardware Based Data Prefetching for High-Performance Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:5, pp:609-623 [Journal]
  32. Tien-Fu Chen, Chia-Ming Hsu, S.-R. Wu
    Flexible Heterogeneous Multicore Architectures for Versatile Media Processing Via Customized Long Instruction Words. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2005, v:15, n:5, pp:659-672 [Journal]
  33. Jui-Chin Chu, Wei-Chun Ku, Shu-Hsuan Chou, Tien-Fu Chen, Jiun-In Guo
    An Embedded Coherent-Multithreading Multimedia Processor and Its Programming Model. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:652-657 [Conf]
  34. Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh
    Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2007, pp:105-119 [Conf]
  35. Jih-Sheng Shen, Kuei-Chung Chang, Tien-Fu Chen
    On a design of crossroad switches for low-power on-chip communication architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  36. Jui-Chin Chu, Chih-Wen Huang, He-Chun Chen, Keng-Po Lu, Ming-Shuan Lee, Jiun-In Guo, Tien-Fu Chen
    Design of customized functional units for the VLIW-based multi-threading processor core targeted at multimedia applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  37. Kuei-Chung Chang, Tien-Fu Chen
    Efficient segment-based video transcoding proxy for mobile multimedia services. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:11, pp:833-845 [Journal]
  38. Tien-Fu Chen, Yi-Min Hwang
    Decoupling of data and tag arrays for on-chip caches. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2002, v:25, n:9-10, pp:437-447 [Journal]

  39. NUDA: a non-uniform debugging architecture and non-intrusive race detection for many-core. [Citation Graph (, )][DBLP]

  40. No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips. [Citation Graph (, )][DBLP]

  41. RunAssert: A non-intrusive run-time assertion for parallel programs debugging. [Citation Graph (, )][DBLP]

  42. Efficient Segment-Based Video Transcoding Proxy for Mobile Multimedia Services. [Citation Graph (, )][DBLP]

  43. Collaborative Multithreading: An Open Scalable Processor Architecture for Embedded Multimedia Applications. [Citation Graph (, )][DBLP]

  44. dIP: A Non-intrusive Debugging IP for Dynamic Data Race Detection in Many-Core. [Citation Graph (, )][DBLP]

  45. VeriC: A semi-hardware description language to bridge the gap between ESL design and RTL models. [Citation Graph (, )][DBLP]

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