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Ruifeng Guo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy
    On Speeding-Up Vector Restoration Based Static Compaction of Test Sequences for Sequential Circuits . [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:467-471 [Conf]
  2. Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz
    On Improving a Fault Simulation Based Test Generator for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:82-0 [Conf]
  3. Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz
    Proptest: A Property Based Test Pattern Generator for Sequential Circuits Using Test Compaction. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:653-659 [Conf]
  4. Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy
    Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:583-0 [Conf]
  5. Ruifeng Guo, Srikanth Venkataraman
    A technique for fault diagnosis of defects in scan chains. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:268-277 [Conf]
  6. Yun Shao, Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz
    The effects of test compaction on fault diagnosis. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1083-1089 [Conf]
  7. Dong Yu, Hu Lin, Ruifeng Guo, Jiangang Yang, Pengfei Xiao
    The Research on Real-Time Middleware for Open Architecture Controller. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2005, pp:80-83 [Conf]
  8. Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy
    On Improving Static Test Compaction for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:111-116 [Conf]
  9. Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy
    A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:260-267 [Conf]
  10. Ruifeng Guo, Subhasish Mitra, Enamul Amyeen, Jinkyu Lee, Srihari Sivaraj, Srikanth Venkataraman
    Evaluation of Test Metrics: Stuck-at, Bridge Coverage Estimate and Gate Exhaustive. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:66-71 [Conf]
  11. Srikanth Venkataraman, Srihari Sivaraj, Enamul Amyeen, Sangbong Lee, Ajay Ojha, Ruifeng Guo
    An Experimental Study of N-Detect Scan ATPG Patterns on a Processor. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:23-30 [Conf]
  12. Xiaoming Yu, Enamul Amyeen, Srikanth Venkataraman, Ruifeng Guo, Irith Pomeranz
    Concurrent Execution of Diagnostic Fault Simulation and Equivalence Identification During Diagnostic Test Generation. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:351-358 [Conf]
  13. Vishnu C. Vimjam, M. Enamul Amyeen, Ruifeng Guo, Srikanth Venkataraman, Michael S. Hsiao, Kai Yang
    Using Scan-Dump Values to Improve Functional-Diagnosis Methodology. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:231-238 [Conf]
  14. Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz
    Reverse-order-restoration-based static test compaction for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:293-304 [Journal]
  15. Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz
    PROPTEST: a property-based test generator for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1080-1091 [Journal]
  16. Ruifeng Guo, Srikanth Venkataraman
    An algorithmic technique for diagnosis of faulty scan chains. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1861-1868 [Journal]
  17. Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo
    Static test compaction for synchronous sequential circuits based on vector restoration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:7, pp:1040-1049 [Journal]

  18. At-Speed Scan Test Method for the Timing Optimization and Calibration. [Citation Graph (, )][DBLP]


  19. Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns. [Citation Graph (, )][DBLP]


  20. On Improving Diagnostic Test Generation for Scan Chain Failures. [Citation Graph (, )][DBLP]


  21. Improving compressed test pattern generation for multiple scan chain failure diagnosis. [Citation Graph (, )][DBLP]


  22. Enhancing the Success Rate of Primary Version While Guaranteeing Fault-Tolerant Capability for Real-Time Systems. [Citation Graph (, )][DBLP]


  23. Scan based speed-path debug for a microprocessor. [Citation Graph (, )][DBLP]


  24. Speed-Path Debug Using At-Speed Scan Test Patterns. [Citation Graph (, )][DBLP]


  25. An Effective RM-Based Scheduling Algorithm for Fault-Tolerant Real-Time Systems. [Citation Graph (, )][DBLP]


  26. Design and Evaluation of Sectional Real-Time Scheduling Algorithms Based on System Load. [Citation Graph (, )][DBLP]


  27. Survey of Scan Chain Diagnosis. [Citation Graph (, )][DBLP]


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