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Jan Madsen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Peter Bjørn-Jørgensen, Jan Madsen
    Critical path driven cosynthesis for heterogeneous target architectures. [Citation Graph (0, 0)][DBLP]
    CODES, 1997, pp:15-22 [Conf]
  2. Jens P. Brage, Jan Madsen
    A codesign case study in computer graphics. [Citation Graph (0, 0)][DBLP]
    CODES, 1994, pp:132-139 [Conf]
  3. Thomas Gleerup, Hans Holten-Lund, Jan Madsen, Steen Pedersen
    Memory architecture for efficient utilization of SDRAM: a case study of the computation/memory access trade-off. [Citation Graph (0, 0)][DBLP]
    CODES, 2000, pp:51-55 [Conf]
  4. Jan Madsen, Peter Bjørn-Jørgensen
    Embedded system synthesis under memory constraints. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:188-192 [Conf]
  5. D. C. R. Jensen, Jan Madsen, Steen Pedersen
    The importance of interfaces: a HW/SW codesign case study. [Citation Graph (0, 0)][DBLP]
    CODES, 1997, pp:87-94 [Conf]
  6. Peter Voigt Knudsen, Jan Madsen
    PACE: A Dynamic Programming Algorithm for Hardware/Software Partitioning. [Citation Graph (0, 0)][DBLP]
    CODES, 1996, pp:85-93 [Conf]
  7. Peter Voigt Knudsen, Jan Madsen
    Communication estimation for hardware/software codesign. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:55-59 [Conf]
  8. Peter Voigt Knudsen, Jan Madsen
    Graph based communication analysis for hardware/software codesign. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:131-135 [Conf]
  9. Jesper Grode, Peter Voigt Knudsen, Jan Madsen
    Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:22-27 [Conf]
  10. Shankar Mahadevan, Federico Angiolini, Michael Storgaard, Rasmus Grøndahl Olsen, Jens Sparsø, Jan Madsen
    A Network Traffic Generator Model for Fast Network-on-Chip Simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:780-785 [Conf]
  11. S. F. Nielsen, Jan Madsen
    Power Constrained High-Level Synthesis of Battery Powered Digital Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11136-11137 [Conf]
  12. S. F. Nielsen, Jens Sparsø, Jan Madsen
    Towards Behavioral Synthesis of Asynchronous Circuits - An Implementation Template Targeting Syntax Directed Compilation. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:298-305 [Conf]
  13. Kashif Virk, Jan Madsen, Andreas Vad Lorentzen, Martin Leopold, Philippe Bonnet
    Design of A Development Platform for HW/SW Codesign ofWireless Integrated Sensor Nodes. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:254-260 [Conf]
  14. Jan Madsen
    Validation and testing of sC++ applications. [Citation Graph (0, 0)][DBLP]
    ECBS, 1997, pp:491-497 [Conf]
  15. Jesper Grode, Jan Madsen
    A Uni.ed Component Modeling Approach for Performance Estimation in Hardware/Software Codesign. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10065-10069 [Conf]
  16. Peter Voigt Knudsen, Jan Madsen
    Integrating Communication Protocol Selection with Partitioning in Hardware/Software Codesign. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:111-116 [Conf]
  17. Jan Madsen, Bjarne Hald
    An approach to interface synthesis. [Citation Graph (0, 0)][DBLP]
    ISSS, 1995, pp:16-21 [Conf]
  18. Shankar Mahadevan, Michael Storgaard, Jan Madsen, Kashif Virk
    ARTS: A System-Level Framework for Modeling MPSoC Components and Analysis of their Causality. [Citation Graph (0, 0)][DBLP]
    MASCOTS, 2005, pp:480-483 [Conf]
  19. Jari Nurmi, Jan Madsen, Erwin Ofner, Jouni Isoaho, Hannu Tenhunen
    The SoC-Mobinet Model in System-on-Chip Education. [Citation Graph (0, 0)][DBLP]
    MSE, 2005, pp:71-72 [Conf]
  20. Jan Madsen, Shankar Mahadevan, Kashif Virk, Mercury Gonzalez
    Network-on-Chip Modeling for System-Level Multiprocessor Simulation. [Citation Graph (0, 0)][DBLP]
    RTSS, 2003, pp:265-274 [Conf]
  21. Jan Madsen
    Single-Level Wiring for CMOS Functional Cells. [Citation Graph (0, 0)][DBLP]
    VLSI, 1991, pp:317-326 [Conf]
  22. Bjarne Hald, Jan Madsen
    Performance Aspects of Gate Matrix Layout. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:226-229 [Conf]
  23. Hans Holten-Lund, Mogens Hvidtfeldt, Jan Madsen, Steen Pedersen
    VRML visualization in a surgery planning and diagnostics application. [Citation Graph (0, 0)][DBLP]
    Web3D, 2000, pp:111-118 [Conf]
  24. Jan Madsen, Jørgen Steensgaard-Madsen, Lars Christensen
    A Sophomore Course in Codesign. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2002, v:35, n:11, pp:108-110 [Journal]
  25. Peter Voigt Knudsen, Jan Madsen
    Integrating communication protocol selection with hardware/software codesign. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:8, pp:1077-1095 [Journal]
  26. Michael R. Hansen, Jan Madsen, Aske Wiid Brekling
    Semantics and Verification of a Language for Modelling Hardware Architectures. [Citation Graph (0, 0)][DBLP]
    Formal Methods and Hybrid Real-Time Systems, 2007, pp:300-319 [Conf]
  27. Jan Madsen, Thomas K. Stidsen, Peter Kjaerulf, Shankar Mahadevan
    Multi-Objective Design Space Exploration of Embedded System Platforms. [Citation Graph (0, 0)][DBLP]
    DIPES, 2006, pp:185-194 [Conf]
  28. Kehuai Wu, Jan Madsen
    COSMOS: A System-Level Modelling and Simulation Framework for Coprocessor-Coupled Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:128-136 [Conf]
  29. Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen
    A Traffic Injection Methodology with Support for System-Level Synchronization. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:145-161 [Conf]
  30. Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Berekovic
    MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:26-38 [Conf]

  31. Tabu search-based synthesis of dynamically reconfigurable digital microfluidic biochips. [Citation Graph (, )][DBLP]

  32. A compositional modelling framework for exploring MPSoC systems. [Citation Graph (, )][DBLP]

  33. Towards Understanding and Managing the Dynamic Behavior of Run-Time Reconfigurable Architectures. [Citation Graph (, )][DBLP]

  34. Modeling shared variables in VHDL. [Citation Graph (, )][DBLP]

  35. Task Mapping and Bandwidth Reservation for Mixed Hard/Soft Fault-Tolerant Embedded Systems. [Citation Graph (, )][DBLP]

  36. Feasibility Study of a Self-healing Hardware Platform. [Citation Graph (, )][DBLP]

  37. A service based estimation method for MPSoC performance modelling. [Citation Graph (, )][DBLP]

  38. Exploration of a digital audio processing platform using a compositional system level performance estimation framework. [Citation Graph (, )][DBLP]

  39. Identifying Inter-task Communication in Shared Memory Programming Models. [Citation Graph (, )][DBLP]

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