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José F. Martínez: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. José F. Martínez, Josep Torrellas
    Speculative synchronization: applying thread-level speculation to explicitly parallel applications. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2002, pp:18-29 [Conf]
  2. M. C. Fernández, O. Delgado, J. I. López, M. A. Luna, José F. Martínez, J. F. B. Pardo, J. M. Peña
    DAMISYS: An Overview. [Citation Graph (0, 0)][DBLP]
    DaWaK, 1999, pp:313-317 [Conf]
  3. Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, José F. Martínez
    Checkpointed Early Load Retirement. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:16-27 [Conf]
  4. Jian Li, José F. Martínez, Michael C. Huang
    The Thrifty Barrier: Energy-Aware Synchronization in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:14-23 [Conf]
  5. José F. Martínez, Josep Torrellas, José Duato
    Improving the performance of bristled CC-NUMA systems using virtual channels and adaptivity. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:202-209 [Conf]
  6. Engin Ipek, José F. Martínez, Bronis R. de Supinski, Sally A. McKee, Martin Schulz
    Dynamic program phase detection in distributed shared-memory multiprocessors. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  7. Marcelo H. Cintra, José F. Martínez, Josep Torrellas
    Architectural support for scalable speculative parallelization in shared-memory multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:13-24 [Conf]
  8. Meyrem Kirman, Nevin Kirman, José F. Martínez
    Cherry-MP: Correctly Integrating Checkpointed Early Resource Recycling in Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:245-256 [Conf]
  9. José F. Martínez, Jose Renau, Michael C. Huang, Milos Prvulovic, Josep Torrellas
    Cherry: checkpointed early resource recycling in out-of-order microprocessors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:3-14 [Conf]
  10. Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, José F. Martínez, Alyssa B. Apsel, Matthew A. Watkins, David H. Albonesi
    Leveraging Optical Technology in Future Bus-based Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:492-503 [Conf]
  11. Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero
    A Case for Resource-conscious Out-of-order Processors. [Citation Graph (0, 0)][DBLP]
    Computer Architecture Letters, 2003, v:2, n:, pp:- [Journal]
  12. José F. Martínez, Josep Torrellas
    Speculative Synchronization: Programmability and Performance for Parallel Codes. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:6, pp:126-134 [Journal]
  13. Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero
    A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2004, v:32, n:3, pp:3-10 [Journal]
  14. Adrián Cristal, Oliverio J. Santana, Mateo Valero, José F. Martínez
    Toward kilo-instruction processors. [Citation Graph (0, 0)][DBLP]
    TACO, 2004, v:1, n:4, pp:389-417 [Journal]
  15. Jian Li, José F. Martínez
    Power-performance considerations of parallel computing on chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    TACO, 2005, v:2, n:4, pp:397-422 [Journal]
  16. Christopher LaFrieda, Engin Ipek, José F. Martínez, Rajit Manohar
    Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor. [Citation Graph (0, 0)][DBLP]
    DSN, 2007, pp:317-326 [Conf]
  17. Engin Ipek, Meyrem Kirman, Nevin Kirman, José F. Martínez
    A Reconfigurable Chip Multiprocessor Architecture to Accommodate Software Diversity. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-6 [Conf]
  18. Engin Ipek, Meyrem Kirman, Nevin Kirman, José F. Martínez
    Core fusion: accommodating software diversity in chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:186-197 [Conf]
  19. Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, José F. Martínez, Alyssa B. Apsel, Matthew A. Watkins, David H. Albonesi
    On-Chip Optical Technology in Future Bus-Based Multicore Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:1, pp:56-66 [Journal]

  20. A power-efficient all-optical on-chip interconnect using wavelength-based oblivious routing. [Citation Graph (, )][DBLP]


  21. Dynamic power-performance adaptation of parallel computation on chip multiprocessors. [Citation Graph (, )][DBLP]


  22. Self-Optimizing Memory Controllers: A Reinforcement Learning Approach. [Citation Graph (, )][DBLP]


  23. Power-Performance Implications of Thread-level Parallelism on Chip Multiprocessors. [Citation Graph (, )][DBLP]


  24. Scavenger: A New Last Level Cache Architecture with Global Block Priority. [Citation Graph (, )][DBLP]


  25. Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach. [Citation Graph (, )][DBLP]


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