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Christos Kozyrakis: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Francois Labonte, Peter R. Mattson, William Thies, Ian Buck, Christos Kozyrakis, Mark Horowitz
    The Stream Virtual Machine. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2004, pp:267-277 [Conf]
  2. Chaiyasit Manovit, Sudheendra Hangal, Hassan Chafi, Austen McDonald, Christos Kozyrakis, Kunle Olukotun
    Testing implementations of transactional memory. [Citation Graph (0, 0)][DBLP]
    PACT, 2006, pp:134-143 [Conf]
  3. Austen McDonald, JaeWoong Chung, Hassan Chafi, Chi Cao Minh, Brian D. Carlstrom, Lance Hammond, Christos Kozyrakis, Kunle Olukotun
    Characterization of TCC on Chip-Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2005, pp:63-74 [Conf]
  4. Lance Hammond, Brian D. Carlstrom, Vicky Wong, Ben Hertzberg, Michael K. Chen, Christos Kozyrakis, Kunle Olukotun
    Programming with transactional coherence and consistency (TCC). [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2004, pp:1-13 [Conf]
  5. JaeWoong Chung, Chi Cao Minh, Austen McDonald, Travis Skare, Hassan Chafi, Brian D. Carlstrom, Christos Kozyrakis, Kunle Olukotun
    Tradeoffs in transactional memory virtualization. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2006, pp:371-381 [Conf]
  6. Ahmad Zmily, Christos Kozyrakis
    Simultaneously improving code size, performance, and energy in embedded processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:224-229 [Conf]
  7. Ahmad Zmily, Earl Killian, Christos Kozyrakis
    Improving Instruction Delivery with a Block-Aware ISA. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2005, pp:530-539 [Conf]
  8. Sewook Wee, Jared Casper, Njuguna Njoroge, Yuriy Teslyar, Daxia Ge, Christos Kozyrakis, Kunle Olukotun
    A practical FPGA-based framework for novel CMP research. [Citation Graph (0, 0)][DBLP]
    FPGA, 2007, pp:116-125 [Conf]
  9. Suzanne Rivoire, Rebecca Schultz, Tomofumi Okuda, Christos Kozyrakis
    Vector Lane Threading. [Citation Graph (0, 0)][DBLP]
    ICPP, 2006, pp:55-64 [Conf]
  10. John Whaley, Christos Kozyrakis
    Heuristics for Profile-Driven Method-Level Speculative Parallelization. [Citation Graph (0, 0)][DBLP]
    ICPP, 2005, pp:147-156 [Conf]
  11. Hassan Chafi, Chi Cao Minh, Austen McDonald, Brian D. Carlstrom, JaeWoong Chung, Lance Hammond, Christos Kozyrakis, Kunle Olukotun
    TAPE: a transactional application profiling environment. [Citation Graph (0, 0)][DBLP]
    ICS, 2005, pp:199-208 [Conf]
  12. Lance Hammond, Vicky Wong, Michael K. Chen, Brian D. Carlstrom, John D. Davis, Ben Hertzberg, Manohar K. Prabhu, Honggo Wijaya, Christos Kozyrakis, Kunle Olukotun
    Transactional Memory Coherence and Consistency. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:102-113 [Conf]
  13. Austen McDonald, JaeWoong Chung, Brian D. Carlstrom, Chi Cao Minh, Hassan Chafi, Christos Kozyrakis, Kunle Olukotun
    Architectural Semantics for Practical Transactional Memory. [Citation Graph (0, 0)][DBLP]
    ISCA, 2006, pp:53-65 [Conf]
  14. Ahmad Zmily, Christos Kozyrakis
    Energy-efficient and high-performance instruction fetch using a block-aware ISA. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:36-41 [Conf]
  15. Ali-Reza Adl-Tabatabai, Christos Kozyrakis, Bratin Saha
    Transactional programming in a multi-core environment. [Citation Graph (0, 0)][DBLP]
    PPOPP, 2007, pp:272- [Conf]
  16. Ali-Reza Adl-Tabatabai, David Dice, Maurice Herlihy, Nir Shavit, Christos Kozyrakis, Christoph von Praun, Michael Scott
    Potential show-stoppers for transactional synchronization. [Citation Graph (0, 0)][DBLP]
    PPOPP, 2007, pp:55- [Conf]
  17. Brian D. Carlstrom, Austen McDonald, Michael Carbin, Christos Kozyrakis, Kunle Olukotun
    Transactional collection classes. [Citation Graph (0, 0)][DBLP]
    PPOPP, 2007, pp:56-67 [Conf]
  18. Lance Hammond, Brian D. Carlstrom, Vicky Wong, Michael K. Chen, Christos Kozyrakis, Kunle Olukotun
    Transactional Coherence and Consistency: Simplifying Parallel Hardware and Software. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:6, pp:92-103 [Journal]
  19. Ali-Reza Adl-Tabatabai, Christos Kozyrakis, Bratin Saha
    Unlocking concurrency. [Citation Graph (0, 0)][DBLP]
    ACM Queue, 2006, v:4, n:10, pp:24-33 [Journal]
  20. Ahmad Zmily, Christos Kozyrakis
    Block-aware instruction set architecture. [Citation Graph (0, 0)][DBLP]
    TACO, 2006, v:3, n:3, pp:327-357 [Journal]
  21. Ahmad Zmily, Christos Kozyrakis
    A low power front-end for embedded processors using a block-aware instruction set. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:267-276 [Conf]
  22. Njuguna Njoroge, Jared Casper, Sewook Wee, Yuriy Teslyar, Daxia Ge, Christos Kozyrakis, Kunle Olukotun
    ATLAS: a chip-multiprocessor with transactional memory support. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:3-8 [Conf]
  23. JongSoo Park, Sung-Boem Park, James D. Balfour, David Black-Schaffer, Christos Kozyrakis, William J. Dally
    Register pointer architecture for efficient embedded processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:600-605 [Conf]
  24. Michael Dalton, Hari Kannan, Christos Kozyrakis
    Raksha: a flexible information flow architecture for software security. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:482-493 [Conf]
  25. Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis
    Comparing memory systems for chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:358-368 [Conf]
  26. Chi Cao Minh, Martin Trautmann, JaeWoong Chung, Austen McDonald, Nathan Bronson, Jared Casper, Christos Kozyrakis, Kunle Olukotun
    An effective hybrid transactional memory system with strong isolation guarantees. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:69-80 [Conf]
  27. Suzanne Rivoire, Mehul A. Shah, Parthasarathy Ranganathan, Christos Kozyrakis
    JouleSort: a balanced energy-efficiency benchmark. [Citation Graph (0, 0)][DBLP]
    SIGMOD Conference, 2007, pp:365-376 [Conf]
  28. Woongki Baek, JaeWoong Chung, Chi Cao Minh, Christos Kozyrakis, Kunle Olukotun
    Towards soft optimization techniques for parallel cognitive applications. [Citation Graph (0, 0)][DBLP]
    SPAA, 2007, pp:59-60 [Conf]
  29. Austen McDonald, Brian D. Carlstrom, JaeWoong Chung, Chi Cao Minh, Hassan Chafi, Christos Kozyrakis, Kunle Olukotun
    Transactional Memory: The Hardware-Software Interface. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:1, pp:67-76 [Journal]

  30. The OpenTM Transactional Application Programming Interface. [Citation Graph (, )][DBLP]


  31. Flexible architectural support for fine-grain scheduling. [Citation Graph (, )][DBLP]


  32. Decoupling Dynamic Information Flow Tracking with a dedicated coprocessor. [Citation Graph (, )][DBLP]


  33. A Scalable, Non-blocking Approach to Transactional Memory. [Citation Graph (, )][DBLP]


  34. Evaluating MapReduce for Multi-core and Multiprocessor Systems. [Citation Graph (, )][DBLP]


  35. Thread-safe dynamic binary translation using transactional memory. [Citation Graph (, )][DBLP]


  36. The common case transactional behavior of multithreaded programs. [Citation Graph (, )][DBLP]


  37. Fast memory snapshot for concurrent programmingwithout synchronization. [Citation Graph (, )][DBLP]


  38. Making nested parallel transactions practical using lightweight hardware support. [Citation Graph (, )][DBLP]


  39. A memory system design framework: creating smart memories. [Citation Graph (, )][DBLP]


  40. Understanding sources of inefficiency in general-purpose chips. [Citation Graph (, )][DBLP]


  41. Hardware Enforcement of Application Security Policies Using Tagged Memory. [Citation Graph (, )][DBLP]


  42. A Comparison of High-Level Full-System Power Models. [Citation Graph (, )][DBLP]


  43. Feedback-directed barrier optimization in a strongly isolated STM. [Citation Graph (, )][DBLP]


  44. Future scaling of processor-memory interfaces. [Citation Graph (, )][DBLP]


  45. Improving software concurrency with hardware-assisted memory snapshot. [Citation Graph (, )][DBLP]


  46. Ased: availability, security, and debugging support usingtransactional memory. [Citation Graph (, )][DBLP]


  47. Implementing and evaluating nested parallel transactions in software transactional memory. [Citation Graph (, )][DBLP]


  48. Real-World Buffer Overflow Protection for Userspace and Kernelspace. [Citation Graph (, )][DBLP]


  49. Phoenix rebirth: Scalable MapReduce on a large-scale shared-memory system. [Citation Graph (, )][DBLP]


  50. STAMP: Stanford Transactional Applications for Multi-Processing. [Citation Graph (, )][DBLP]


  51. Evaluating Bufferless Flow Control for On-chip Networks. [Citation Graph (, )][DBLP]


  52. Transactional memory. [Citation Graph (, )][DBLP]


  53. Models and Metrics to Enable Energy-Efficiency Optimizations. [Citation Graph (, )][DBLP]


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