The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
Margaret Martonosi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Per Stenström, Erik Hagersten, David J. Lilja, Margaret Martonosi, Madan Venugopal
    Trends in Shared Memory Multiprocessing. [Citation Graph (1, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:12, pp:44-50 [Journal]
  2. Kevin Skadron, Margaret Martonosi, Douglas W. Clark
    A Taxonomy of Branch Mispredictions, and Alloyed Prediction as a Robust Solution to Wrong-History Mispredictions. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:199-206 [Conf]
  3. Somnath Ghosh, Margaret Martonosi, Sharad Malik
    Precise Miss Analysis for Program Transformations with Caches of Arbitrary Associativity. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1998, pp:228-239 [Conf]
  4. Philo Juang, Hidekazu Oki, Yong Wang, Margaret Martonosi, Li-Shiuan Peh, Daniel Rubenstein
    Energy-efficient computing for wildlife tracking: design tradeoffs and early experiences with ZebraNet. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2002, pp:96-107 [Conf]
  5. Qiang Wu, Philo Juang, Margaret Martonosi, Douglas W. Clark
    Formal online methods for voltage/frequency control in multiple clock domain microprocessors. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2004, pp:248-259 [Conf]
  6. David Brooks, Margaret Martonosi
    Implementing Application-Specific Cache-Coherence Protocols in Configurable Hardware. [Citation Graph (0, 0)][DBLP]
    CANPC, 1999, pp:181-195 [Conf]
  7. Fen Xie, Margaret Martonosi, Sharad Malik
    Efficient behavior-driven runtime dynamic voltage scaling policies. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:105-110 [Conf]
  8. Sharad Malik, Margaret Martonosi, Yau-Tsun Steven Li
    Static Timing Analysis of Embedded Software. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:147-152 [Conf]
  9. Peixin Zhong, Pranav Ashar, Sharad Malik, Margaret Martonosi
    Using Reconfigurable Computing Techniques to Accelerate Problems in the CAD Domain: A Case Study with Boolean Satisfiability. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:194-199 [Conf]
  10. Darko Stefanovic, Margaret Martonosi
    Limits and Graph Structure of Available Instruction-Level Parallelism (Research Note). [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2000, pp:1018-1022 [Conf]
  11. Zhen Luo, Margaret Martonosi, Pranav Ashar
    An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:158-167 [Conf]
  12. Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik
    Accelerating Boolean Satisfiability with Configurable Hardware. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:186-195 [Conf]
  13. Darko Stefanovic, Margaret Martonosi
    On Availability of Bit-Narrow Operations in General-Purpose Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:412-421 [Conf]
  14. Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik
    Solving Boolean Satisfiability with Dynamic Hardware Configurations. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:326-335 [Conf]
  15. David Brooks, Margaret Martonosi
    Dynamic Thermal Management for High-Performance Microprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:171-0 [Conf]
  16. David Brooks, Margaret Martonosi
    Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:13-22 [Conf]
  17. Zhigang Hu, Margaret Martonosi, Stefanos Kaxiras
    TCP: Tag Correlating Prefetchers. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:317-326 [Conf]
  18. Russ Joseph, David Brooks, Margaret Martonosi
    Control Techniques to Eliminate Voltage Emergencies in High Performance Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:79-90 [Conf]
  19. Russ Joseph, Zhigang Hu, Margaret Martonosi
    Wavelet Analysis for Microprocessor Design: Experiences with Wavelet-Based dI/dt Characterization. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:36-47 [Conf]
  20. Qiang Wu, Philo Juang, Margaret Martonosi, Douglas W. Clark
    Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:178-189 [Conf]
  21. Zhigang Hu, Philo Juang, Kevin Skadron, Douglas W. Clark, Margaret Martonosi
    Applying Decay Strategies to Branch Predictors for Leakage Energy Savings. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:442-445 [Conf]
  22. Margaret Martonosi, Anoop Gupta
    Tradeoffs in Message Passing and Shared Memory Implementations of a Standard Cell Router. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1989, pp:88-96 [Conf]
  23. Pritpal S. Ahuja, Kevin Skadron, Margaret Martonosi, Douglas W. Clark
    Multipath Execution: Opportunities and Limits. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1998, pp:101-108 [Conf]
  24. Somnath Ghosh, Margaret Martonosi, Sharad Malik
    Automated cache optimizations using CME driven diagnosis. [Citation Graph (0, 0)][DBLP]
    ICS, 2000, pp:316-326 [Conf]
  25. Somnath Ghosh, Margaret Martonosi, Sharad Malik
    Cache Miss Equations: An Analytical Representation of Cache Misses. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1997, pp:317-324 [Conf]
  26. Cheng Liao, Dongming Jiang, Liviu Iftode, Margaret Martonosi, Douglas W. Clark
    Monitoring Shared Virtual Memory Performance on a Myrinet-based PC Cluster. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1998, pp:251-258 [Conf]
  27. Xianfeng Zhou, Margaret Martonosi
    Augmenting Modern Superscalar Architectures with Configurable Extended Instructions. [Citation Graph (0, 0)][DBLP]
    IPDPS Workshops, 2000, pp:941-950 [Conf]
  28. Matthias A. Blumrich, Richard Alpert, Yuqun Chen, Douglas W. Clark, Stefanos N. Damianakis, Cezary Dubnicki, Edward W. Felten, Liviu Iftode, Kai Li, Margaret Martonosi, Robert A. Shillner
    Design Choices in the SHRIMP System: An Empirical Study. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:330-341 [Conf]
  29. David Brooks, Vivek Tiwari, Margaret Martonosi
    Wattch: a framework for architectural-level power analysis and optimizations. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:83-94 [Conf]
  30. James Donald, Margaret Martonosi
    Techniques for Multicore Thermal Management: Classification and New Exploration. [Citation Graph (0, 0)][DBLP]
    ISCA, 2006, pp:78-88 [Conf]
  31. Mark Horowitz, Margaret Martonosi, Todd C. Mowry, Michael D. Smith
    Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:260-270 [Conf]
  32. Zhigang Hu, Margaret Martonosi, Stefanos Kaxiras
    Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:209-220 [Conf]
  33. Stefanos Kaxiras, Zhigang Hu, Margaret Martonosi
    Cache decay: exploiting generational behavior to reduce cache leakage power. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:240-251 [Conf]
  34. Gilberto Contreras, Margaret Martonosi
    Power prediction for intel XScale processors using performance monitoring unit events. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:221-226 [Conf]
  35. Zhigang Hu, Philo Juang, Phil Diodato, Stefanos Kaxiras, Kevin Skadron, Margaret Martonosi, Douglas W. Clark
    Managing leakage for transient data: decay and quasi-static 4T memory cells. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:52-55 [Conf]
  36. Russ Joseph, Margaret Martonosi
    Run-time power estimation in high performance microprocessors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:135-140 [Conf]
  37. Philo Juang, Qiang Wu, Li-Shiuan Peh, Margaret Martonosi, Douglas W. Clark
    Coordinated, distributed, formal energy management of chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:127-130 [Conf]
  38. Fen Xie, Margaret Martonosi, Sharad Malik
    Bounds on power savings using runtime dynamic voltage scaling: an exact algorithm and a linear-time heuristic approximation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:287-292 [Conf]
  39. James Donald, Margaret Martonosi
    Power efficiency for variation-tolerant multicore processors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:304-309 [Conf]
  40. Russ Joseph, Margaret Martonosi, Zhigang Hu
    Spectral analysis for characterizing program power and performance. [Citation Graph (0, 0)][DBLP]
    ISPASS, 2004, pp:151-160 [Conf]
  41. Margaret Martonosi
    Embedded systems in the wild: ZebraNet software, hardware, and deployment experiences. [Citation Graph (0, 0)][DBLP]
    LCTES, 2006, pp:1- [Conf]
  42. Gilberto Contreras, Margaret Martonosi, Jinzhan Peng, Roy Ju, Guei-Yuan Lueh
    XTREM: a power simulator for the Intel XScale® core. [Citation Graph (0, 0)][DBLP]
    LCTES, 2004, pp:115-125 [Conf]
  43. Yong Wang, Margaret Martonosi, Li-Shiuan Peh
    Situation-Aware Caching Strategies in Highly Varying Mobile Networks. [Citation Graph (0, 0)][DBLP]
    MASCOTS, 2006, pp:265-274 [Conf]
  44. Canturk Isci, Margaret Martonosi
    Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:93-104 [Conf]
  45. Kevin Skadron, Pritpal S. Ahuja, Margaret Martonosi, Douglas W. Clark
    Improving Prediction for Procedure Returns with Return-address-stack Repair Mechanisms. [Citation Graph (0, 0)][DBLP]
    MICRO, 1998, pp:259-271 [Conf]
  46. Qiang Wu, Margaret Martonosi, Douglas W. Clark, Vijay Janapa Reddi, Dan Connors, Youfeng Wu, Jin Lee, David Brooks
    A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:271-282 [Conf]
  47. Canturk Isci, Alper Buyuktosunoglu, Chen-Yong Cher, Pradip Bose, Margaret Martonosi
    An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:347-358 [Conf]
  48. Canturk Isci, Gilberto Contreras, Margaret Martonosi
    Live, Runtime Phase Monitoring and Prediction on Real Systems with Application to Dynamic Power Management. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:359-370 [Conf]
  49. Ting Liu, Christopher M. Sadler, Pei Zhang, Margaret Martonosi
    Implementing Software on Resource-Constrained Mobile Sensors: Experiences with Impala and ZebraNet. [Citation Graph (0, 0)][DBLP]
    MobiSys, 2004, pp:- [Conf]
  50. David Brooks, Margaret Martonosi, John-David Wellman, Pradip Bose
    Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor. [Citation Graph (0, 0)][DBLP]
    PACS, 2000, pp:126-136 [Conf]
  51. Fen Xie, Margaret Martonosi, Sharad Malik
    Compile-time dynamic voltage scaling settings: opportunities and limits. [Citation Graph (0, 0)][DBLP]
    PLDI, 2003, pp:49-62 [Conf]
  52. Ting Liu, Margaret Martonosi
    Impala: a middleware system for managing autonomic, parallel sensor systems. [Citation Graph (0, 0)][DBLP]
    PPOPP, 2003, pp:107-118 [Conf]
  53. Hongli Zhang, Margaret Martonosi
    A Mathematical Cache Miss Analysis for Pointer Data Structures. [Citation Graph (0, 0)][DBLP]
    PPSC, 2001, pp:- [Conf]
  54. Yong Wang, Margaret Martonosi, Li-Shiuan Peh
    A new scheme on link quality prediction and its applications to metric-based routing. [Citation Graph (0, 0)][DBLP]
    SenSys, 2005, pp:288-289 [Conf]
  55. Pei Zhang, Christopher M. Sadler, Stephen A. Lyon, Margaret Martonosi
    Hardware design experiences in ZebraNet. [Citation Graph (0, 0)][DBLP]
    SenSys, 2004, pp:227-238 [Conf]
  56. Christopher M. Sadler, Margaret Martonosi
    Data compression algorithms for energy-constrained devices in delay tolerant networks. [Citation Graph (0, 0)][DBLP]
    SenSys, 2006, pp:265-278 [Conf]
  57. Pei Zhang, Margaret Martonosi
    Energy adaptation techniques to optimize data delivery in store-and-forward sensor networks. [Citation Graph (0, 0)][DBLP]
    SenSys, 2006, pp:405-406 [Conf]
  58. Cheng Liao, Margaret Martonosi, Douglas W. Clark
    An Adaptive Globally-Synchronizing Clock Algorithm and its Implementation on a Myrinet-based PC Cluster. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1999, pp:200-201 [Conf]
  59. Margaret Martonosi, Anoop Gupta, Thomas E. Anderson
    MemSpy: Analyzing Memory System Bottlenecks in Programs. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1992, pp:1-12 [Conf]
  60. Margaret Martonosi, Anoop Gupta, Thomas E. Anderson
    Effectiveness of Trace Sampling for Performance Debugging Tools. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1993, pp:248-259 [Conf]
  61. Margaret Martonosi, David Ofelt, Mark Heinrich
    Integrating Performance Monitoring and Communication in Parallel Computers. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1996, pp:138-147 [Conf]
  62. Cheng Liao, Margaret Martonosi, Douglas W. Clark
    Experience with an Adaptive Globally-Synchronizing Clock Algorithm. [Citation Graph (0, 0)][DBLP]
    SPAA, 1999, pp:106-114 [Conf]
  63. Per Stenström, Erik Hagersten, David J. Lilja, Margaret Martonosi, Madan Venugopal
    Shared-memory multiprocessing: Current state and future directions. [Citation Graph (0, 0)][DBLP]
    Advances in Computers, 2000, v:53, n:, pp:2-55 [Journal]
  64. Philo Juang, Phil Diodato, Stefanos Kaxiras, Kevin Skadron, Zhigang Hu, Margaret Martonosi, Douglas W. Clark
    Implementing Decay Techniques using 4T Quasi-Static Memory Cells. [Citation Graph (0, 0)][DBLP]
    Computer Architecture Letters, 2002, v:1, n:, pp:- [Journal]
  65. Margaret Martonosi, Anoop Gupta, Thomas E. Anderson
    Tuning Memory Performance of Sequential and Parallel Programs. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1995, v:28, n:4, pp:32-40 [Journal]
  66. Kevin Skadron, Margaret Martonosi, David I. August, Mark D. Hill, David J. Lilja, Vijay S. Pai
    Challenges in Computer Architecture Evaluation. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:8, pp:30-36 [Journal]
  67. Mary W. Hall, Margaret Martonosi
    Adaptive parallelism in compiler-parallelized code. [Citation Graph (0, 0)][DBLP]
    Concurrency - Practice and Experience, 1998, v:10, n:14, pp:1235-1250 [Journal]
  68. Kevin Skadron, Margaret Martonosi, Douglas W. Clark
    Speculative Updates of Local and Global Branch History: A Quantitative Analysis. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2000, v:2, n:, pp:- [Journal]
  69. Canturk Isci, Alper Buyuktosunoglu, Margaret Martonosi
    Long-Term Workload Phases: Duration Predictions and Applications to DVFS. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:5, pp:39-51 [Journal]
  70. Qiang Wu, Philo Juang, Margaret Martonosi, Li-Shiuan Peh, Douglas W. Clark
    Formal Control Techniques for Power-Performance Management. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:5, pp:52-62 [Journal]
  71. Qiang Wu, Margaret Martonosi, Douglas W. Clark, Vijay Janapa Reddi, Dan Connors, Youfeng Wu, Jin Lee, David Brooks
    Dynamic-Compiler-Driven Control for Microprocessor Energy and Performance. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:1, pp:119-129 [Journal]
  72. Julia Chen, Philo Juang, Kevin Ko, Gilberto Contreras, David Penry, Ram Rangan, Adam Stoler, Li-Shiuan Peh, Margaret Martonosi
    Hardware-modulated parallelism in chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:4, pp:54-63 [Journal]
  73. David Brooks, Pradip Bose, Margaret Martonosi
    Power-performance simulation: design and validation strategies. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS Performance Evaluation Review, 2004, v:31, n:4, pp:13-18 [Journal]
  74. Yong Wang, Margaret Martonosi, Li-Shiuan Peh
    MARio: mobility-adaptive routing using route lifetime abstractions in mobile ad hoc networks. [Citation Graph (0, 0)][DBLP]
    Mobile Computing and Communications Review, 2004, v:8, n:4, pp:77-81 [Journal]
  75. Philo Juang, Kevin Skadron, Margaret Martonosi, Zhigang Hu, Douglas W. Clark, Phil Diodato, Stefanos Kaxiras
    Implementing branch-predictor decay using quasi-static memory cells. [Citation Graph (0, 0)][DBLP]
    TACO, 2004, v:1, n:2, pp:180-219 [Journal]
  76. Fen Xie, Margaret Martonosi, Sharad Malik
    Intraprogram dynamic voltage scaling: Bounding opportunities with analytic modeling. [Citation Graph (0, 0)][DBLP]
    TACO, 2004, v:1, n:3, pp:323-367 [Journal]
  77. Zhen Luo, Margaret Martonosi
    Accelerating Pipelined Integer and Floating-Point Accumulations in Configurable Hardware with Delayed Addition Techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:3, pp:208-218 [Journal]
  78. Kevin Skadron, Pritpal A. Ahuja, Margaret Martonosi, Douglas W. Clark
    Branch Prediction, Instruction-Window Size, and Cache Size: Performance Trade-Offs and Simulation Techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:11, pp:1260-1281 [Journal]
  79. Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik
    Using configurable computing to accelerate Boolean satisfiability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:861-868 [Journal]
  80. Gilberto Contreras, Margaret Martonosi, Jinzhang Peng, Guei-Yuan Lueh, Roy Ju
    The XTREM power and performance simulator for the Intel XScale core: Design and experiences. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2007, v:6, n:1, pp:- [Journal]
  81. David Brooks, Margaret Martonosi
    Value-based clock gating and operation packing: dynamic strategies for improving processor power and performance. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Syst., 2000, v:18, n:2, pp:89-126 [Journal]
  82. Mark Horowitz, Margaret Martonosi, Todd C. Mowry, Michael D. Smith
    Informing Memory Operations: Memory Performance Feedback Mechanisms and Their Applications. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Syst., 1998, v:16, n:2, pp:170-205 [Journal]
  83. Zhigang Hu, Stefanos Kaxiras, Margaret Martonosi
    Let caches decay: reducing leakage energy via exploitation of cache generational behavior. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Syst., 2002, v:20, n:2, pp:161-190 [Journal]
  84. Somnath Ghosh, Margaret Martonosi, Sharad Malik
    Cache miss equations: a compiler framework for analyzing and tuning memory behavior. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 1999, v:21, n:4, pp:703-746 [Journal]
  85. Evan Torrie, Margaret Martonosi, Chau-Wen Tseng, Mary W. Hall
    Characterizing the Memory Behavior of Compiler-Parallelized Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1996, v:7, n:12, pp:1224-1237 [Journal]
  86. Eric Chi, Stephen A. Lyon, Margaret Martonosi
    Tailoring quantum architectures to implementation style: a quantum computer for mobile and persistent qubits. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:198-209 [Conf]
  87. Christopher M. Sadler, Margaret Martonosi
    Dali: a communication-centric data abstraction layer for energy-constrained devices in mobile sensor networks. [Citation Graph (0, 0)][DBLP]
    MobiSys, 2007, pp:99-112 [Conf]
  88. Gilberto Contreras, Margaret Martonosi
    Techniques for Real-System Characterization of Java Virtual Machine Energy and Power Behavior. [Citation Graph (0, 0)][DBLP]
    IISWC, 2006, pp:29-38 [Conf]

  89. Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors. [Citation Graph (, )][DBLP]


  90. Inter-core cooperative TLB for chip multiprocessors. [Citation Graph (, )][DBLP]


  91. ZebraNet and beyond: applications and systems support for mobile, dynamic networks. [Citation Graph (, )][DBLP]


  92. Phase characterization for power: evaluating control-flow-based and event-counter-based techniques. [Citation Graph (, )][DBLP]


  93. LOCALE: Collaborative Localization Estimation for Sparse Mobile Sensor Networks. [Citation Graph (, )][DBLP]


  94. Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors. [Citation Graph (, )][DBLP]


  95. Full-system chip multiprocessor power evaluations using FPGA-based emulation. [Citation Graph (, )][DBLP]


  96. Middleware for long-term deployment of delay-tolerant sensor networks. [Citation Graph (, )][DBLP]


  97. Potential for collaborative caching and prefetching in largely-disconnected villages. [Citation Graph (, )][DBLP]


  98. Managing the cost, energy consumption, and carbon footprint of internet services. [Citation Graph (, )][DBLP]


  99. Location-based trust for mobile user-generated content: applications, challenges and implementations. [Citation Graph (, )][DBLP]


  100. Characterizing and improving the performance of Intel Threading Building Blocks. [Citation Graph (, )][DBLP]


  101. An Efficient, Practical Parallelization Methodology for Multicore Architecture Simulation. [Citation Graph (, )][DBLP]


Search in 0.005secs, Finished in 0.607secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002