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Javier D. Bruguera: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Paula N. Mallón, Montserrat Bóo, Margarita Amor, Javier D. Bruguera
    Concentric Strips: Algorithms and Architecture for the Compression/Decompression of Triangle Meshes. [Citation Graph (0, 0)][DBLP]
    3DPVT, 2002, pp:380-383 [Conf]
  2. Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata
    Redundant CORDIC Rotator Based on Parallel Prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1995, pp:172-179 [Conf]
  3. Elisardo Antelo, Tomás Lang, Javier D. Bruguera
    Very-High Radix CORDIC Vectoring with Scalings and Selection by Rounding. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1999, pp:204-0 [Conf]
  4. Javier D. Bruguera, Tomás Lang
    Using the Reverse-Carry Approach for Double Datapath Floating-Point Addition. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:203-210 [Conf]
  5. Javier D. Bruguera, Tomás Lang
    Floating-Point Fused Multiply-Add: Reduced Latency for Floating-Point Addition. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2005, pp:42-51 [Conf]
  6. José-Alejandro Piñeiro, Javier D. Bruguera, Jean-Michel Muller
    Faithful Powering Computation Using Table Look-Up and a Fused Accumulation Tree. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2001, pp:40-0 [Conf]
  7. José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera
    High-Radix Iterative Algorithm for Powering Computation. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2003, pp:204-211 [Conf]
  8. Montserrat Bóo, Francisco Argüello, Javier D. Bruguera, Emilio L. Zapata
    High-Speed Viterbi Decoder: An Efficient Scheduling Method to Exploit the Pipelining. [Citation Graph (0, 0)][DBLP]
    ASAP, 1996, pp:165-0 [Conf]
  9. Roberto R. Osorio, Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata
    Digit On-line Large Radix CORDIC Rotator. [Citation Graph (0, 0)][DBLP]
    ASAP, 1995, pp:246-257 [Conf]
  10. Roberto R. Osorio, Javier D. Bruguera
    New arithmetic coder/decoder architectures based on pipelining. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:106-115 [Conf]
  11. José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera
    High-Radix Logarithm with Selection by Rounding. [Citation Graph (0, 0)][DBLP]
    ASAP, 2002, pp:101-110 [Conf]
  12. Julio Villalba, J. C. Arrabal, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera
    Radix-4 Vectoring Cordic Algorithm And Architectures. [Citation Graph (0, 0)][DBLP]
    ASAP, 1996, pp:55-64 [Conf]
  13. Julio Villalba, J. A. Hidalgo, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera
    CORDIC Architectures with Parallel Compensation of the Scale Factor. [Citation Graph (0, 0)][DBLP]
    ASAP, 1995, pp:258-269 [Conf]
  14. Roberto R. Osorio, Javier D. Bruguera
    Arithmetic Coding Architecture for H.264/AVC CABAC Compression System. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:62-69 [Conf]
  15. Roberto R. Osorio, Javier D. Bruguera
    A New Architecture for fast Arithmetic Coding in H.264 Advanced Video Coder. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:298-305 [Conf]
  16. José-Alejandro Piñeiro, Javier D. Bruguera, Jean-Michel Muller
    FPGA Implementation of a Faithful Polynomial Approximation for Powering Function Computation. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:262-269 [Conf]
  17. D. Piso, José-Alejandro Piñeiro, Javier D. Bruguera
    Analysis of the Impact of Different Methods for Division/Square Root Computation in the Performance of a Superscalar Microprocessor. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:218-225 [Conf]
  18. Roberto R. Osorio, Javier D. Bruguera
    A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:269-274 [Conf]
  19. Viay Holimath, Javier D. Bruguera
    A Linear Convergent Functional Iterative DivisionWithout a Look-Up Table. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:236-239 [Conf]
  20. Javier D. Bruguera, Roberto R. Osorio
    A Unified Architecture for H.264 Multiple Block-Size DCT with Fast and Low Cost Quantization. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:407-414 [Conf]
  21. Paula N. Mallón, Montserrat Bóo, Javier D. Bruguera
    Parallel Architecture for Conversion of NURBS Curves to Bézier Curves. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1324-1331 [Conf]
  22. Roberto R. Osorio, Montserrat Bóo, Javier D. Bruguera
    Arithmetic Image Coding/Decoding Architecture Based on a Cache Memory. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10139-0 [Conf]
  23. Mercedes Péon, Roberto R. Osorio, Javier D. Bruguera
    A VLSI implementation of an arithmetic coder for image compression. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1997, pp:591-0 [Conf]
  24. Ángel del Río, Montserrat Bóo, Margarita Amor, Javier D. Bruguera
    Hardware Implementation of the Subdivision Loop Algorithm. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2002, pp:189-199 [Conf]
  25. Elisardo Antelo, Javier D. Bruguera, Tomás Lang, Julio Villalba, Emilio L. Zapata
    High Radix Cordic Rotation Based on Selection by Rounding. [Citation Graph (0, 0)][DBLP]
    Euro-Par, Vol. II, 1996, pp:155-164 [Conf]
  26. Paula N. Mallón, Montserrat Bóo, Javier D. Bruguera
    Implementation of a NURBS to Bézier Conversor with Constant Latency. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:213-222 [Conf]
  27. Juan Touriño, Francisco F. Rivera, Carlos Álvarez, Cesar M. Dans, Jorge Parapar, Ramon Doallo, Marcos Boullón, Javier D. Bruguera, Rafael Crecente, Xesús P. González
    COPA: a GIS-based Tool for Land Consolidation Projects. [Citation Graph (0, 0)][DBLP]
    ACM-GIS, 2001, pp:53-58 [Conf]
  28. José Carlos Mouriño, David E. Singh, María J. Martín, J. M. Eiroa, Francisco F. Rivera, Ramon Doallo, Javier D. Bruguera
    Parallelization of the STEM-II Air Quality Model. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 2001, pp:543-546 [Conf]
  29. Javier D. Bruguera, Tomás Lang
    Multilevel Reverse-Carry Adder. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:155-162 [Conf]
  30. Tomás Lang, Javier D. Bruguera
    Floating-Point Fused Multiply-Add with Reduced Latency. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:145-0 [Conf]
  31. Tomás Lang, Javier D. Bruguera
    Multilevel Reverse-Carry Computation for Comparison and for Sign and Overflow Detection in Addition. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:73-79 [Conf]
  32. José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera
    Analysis of the Tradeoffs for the Implementation of a High-Radix Logarithm. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:132-137 [Conf]
  33. José Carlos Mouriño, María J. Martín, Ramon Doallo, David E. Singh, Francisco F. Rivera, Javier D. Bruguera
    The STEM-II Air Quality Model on a Distributed Memory System. [Citation Graph (0, 0)][DBLP]
    ICPP Workshops, 2001, pp:85-92 [Conf]
  34. José-Alejandro Piñeiro, Javier D. Bruguera, Milos D. Ercegovac
    On-line high-radix exponential with selection by rounding. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:121-124 [Conf]
  35. F. J. Espino, Montserrat Bóo, Margarita Amor, Javier D. Bruguera
    Adaptive Tessellation of NURBS Surfaces. [Citation Graph (0, 0)][DBLP]
    WSCG, 2003, pp:- [Conf]
  36. F. J. Espino, Montserrat Bóo, Margarita Amor, Javier D. Bruguera
    Adaptive Tessellation of Bezier Surfaces Based on Displacement Maps. [Citation Graph (0, 0)][DBLP]
    WSCG (Short Papers), 2005, pp:29-32 [Conf]
  37. Paula N. Mallón, Montserrat Bóo, Margarita Amor, Javier D. Bruguera
    Algorithms and Hardware for Data Compression in Point Rendering Applications. [Citation Graph (0, 0)][DBLP]
    WSCG (Short Papers), 2004, pp:173-180 [Conf]
  38. Oscar G. Plata, Javier D. Bruguera, Francisco F. Rivera, Ramon Doallo, Emilio L. Zapata
    ACLE: A Software Package for SIMD Computer Simulation. [Citation Graph (0, 0)][DBLP]
    Comput. J., 1990, v:33, n:3, pp:194-203 [Journal]
  39. Juan Touriño, Jorge Parapar, Ramon Doallo, Marcos Boullón, Francisco F. Rivera, Javier D. Bruguera, Xesús P. González, Rafael Crecente, Carlos Álvarez
    Research Article: A GIS-embedded system to support land consolidation plans in Galicia. [Citation Graph (0, 0)][DBLP]
    International Journal of Geographical Information Science, 2003, v:17, n:4, pp:377-396 [Journal]
  40. Francisco Argüello, Javier D. Bruguera, Emilio L. Zapata
    A Parallel Architecture for the Self-Sorting FFT Algorithm. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1995, v:31, n:1, pp:88-97 [Journal]
  41. F. J. Espino, Montserrat Bóo, Margarita Amor, Javier D. Bruguera
    Hardware support for adaptive tessellation of Bézier surfaces based on local tests. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:4, pp:233-250 [Journal]
  42. D. Piso, José-Alejandro Piñeiro, Javier D. Bruguera
    Analysis of the impact of different methods for division/square root computation in the performance of a superscalar microprocessor. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:12-15, pp:543-555 [Journal]
  43. Javier D. Bruguera, Elisardo Antelo, Emilio L. Zapata
    Design of a Pipelined Radix 4 CORDIC Processor. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1993, v:19, n:7, pp:729-744 [Journal]
  44. Inmaculada García, Juan J. Merelo Guervós, Javier D. Bruguera, Emilio L. Zapata
    Parallel quadrant interlocking factorization on hypercube computers. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1990, v:15, n:1-3, pp:87-100 [Journal]
  45. María J. Martín, David E. Singh, José Carlos Mouriño, Francisco F. Rivera, Ramon Doallo, Javier D. Bruguera
    High performance air pollution modeling for a power plant environment. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 2003, v:29, n:11-12, pp:1763-1790 [Journal]
  46. Francisco F. Rivera, Ramon Doallo, Javier D. Bruguera, Emilio L. Zapata, R. Peskin
    Gaussian elimination with pivoting on hypercubes. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1990, v:14, n:1, pp:51-60 [Journal]
  47. Elisardo Antelo, Javier D. Bruguera, Tomás Lang, Emilio L. Zapata
    Error Analysis and Reduction for Angle Calculation Using the CORDIC Algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:11, pp:1264-1271 [Journal]
  48. Elisardo Antelo, Javier D. Bruguera, Emilio L. Zapata
    Unified Mixed Radix 2-4 Redundant CORDIC Processor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:9, pp:1068-1073 [Journal]
  49. Elisardo Antelo, Tomás Lang, Javier D. Bruguera
    Very-High Radix Circular CORDIC: Vectoring and Unified Rotation/Vectoring. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:7, pp:727-739 [Journal]
  50. Elisardo Antelo, Tomás Lang, Javier D. Bruguera
    Computation of sqrt(x/d) in a Very High Radix Combined Division/Square-Root Unit with Scaling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:2, pp:152-161 [Journal]
  51. Elisardo Antelo, Julio Villalba, Javier D. Bruguera, Emilio L. Zapata
    High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:8, pp:855-870 [Journal]
  52. Javier D. Bruguera, Tomás Lang
    Leading-One Prediction with Concurrent Position Correction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:10, pp:1083-1097 [Journal]
  53. Tomás Lang, Javier D. Bruguera
    Floating-Point Multiply-Add-Fused with Reduced Latency. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:8, pp:988-1003 [Journal]
  54. José-Alejandro Piñeiro, Javier D. Bruguera
    High-Speed Double-Precision Computation of Reciprocal, Division, Square Root and Inverse Square Root. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:12, pp:1377-1388 [Journal]
  55. José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera
    Algorithm and Architecture for Logarithm, Exponential, and Powering Computation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:9, pp:1085-1096 [Journal]
  56. José-Alejandro Piñeiro, Stuart F. Oberman, Jean-Michel Muller, Javier D. Bruguera
    High-Speed Function Approximation Using a Minimax Quadratic Interpolator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:3, pp:304-318 [Journal]
  57. Francisco Argüello, Javier D. Bruguera, Ramon Doallo, Emilio L. Zapata
    Parallel Architecture for Fast Transforms with Trigonometric Kernel. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1994, v:5, n:10, pp:1091-1099 [Journal]
  58. Paolo Montuschi, Javier D. Bruguera, Luigi Ciminiera, José-Alejandro Piñeiro
    A Digit-by-Digit Algorithm for mth Root Extraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:12, pp:1696-1706 [Journal]
  59. Roberto R. Osorio, Javier D. Bruguera
    High-Throughput Architecture for H.264/AVC CABAC Compression System. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2006, v:16, n:11, pp:1376-1384 [Journal]
  60. Elisardo Antelo, Montserrat Bóo, Javier D. Bruguera, Emilio L. Zapata
    A novel design of a two operand normalization circuit. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:173-176 [Journal]
  61. Javier D. Bruguera, Tomás Lang
    Multilevel reverse most-significant carry computation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:959-962 [Journal]

  62. Entropy Coding on a Programmable Processor Array for Multimedia SoC. [Citation Graph (, )][DBLP]


  63. An FPGA architecture for CABAC decoding in manycore systems. [Citation Graph (, )][DBLP]


  64. A New Rounding Algorithm for Variable Latency Division and Square Root Implementations. [Citation Graph (, )][DBLP]


  65. High Performance Image Processing on a Massively Parallel Processor Array. [Citation Graph (, )][DBLP]


  66. Variable Latency Rounding for Golschmidt Algorithm with Parallel Remainder Estimation. [Citation Graph (, )][DBLP]


  67. Topic 10: Parallel Numerical Algorithms. [Citation Graph (, )][DBLP]


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