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Publications of Author

1. Asim J. Al-Khalili, Yong Zhu, Dhamin Al-Khalili
   A Module Generator for Optimized CMOS Buffers. [Citation Graph (0, 0)][DBLP]
   DAC, 1989, pp:245-250 [Conf]
   
2. Jason Coppens, Dhamin Al-Khalili, Come Rozon
   VHDL Modelling and Analysis of Fault Secure Systems. [Citation Graph (0, 0)][DBLP]
   DATE, 1998, pp:148-152 [Conf]
   
3. Dhamin Al-Khalili, Saman Adham, Come Rozon, Moazzem Hossain, D. Racz
   Comprehensive Defect Analysis and Defect Coverage of CMOS Circuits. [Citation Graph (0, 0)][DBLP]
   DFT, 1998, pp:84-92 [Conf]
   
4. J. M. P. Langlois, Dhamin Al-Khalili
   A low power direct digital frequency synthesizer with 60 dBc spectral purity. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2002, pp:166-171 [Conf]
   
5. Donald B. Shaw, Dhamin Al-Khalili, Come Rozon
   Accurate CMOS Bridge Fault Modeling with Neural Network-Based VHDL Saboteurs. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2001, pp:531-536 [Conf]
   
6. R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili
   A Low Power Approach to Floating Point Adder Design. [Citation Graph (0, 0)][DBLP]
   ICCD, 1997, pp:178-185 [Conf]
   
7. R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili
   An IEEE Compliant Floating Point MAF. [Citation Graph (0, 0)][DBLP]
   VLSI, 1999, pp:149-160 [Conf]
   
8. Michael Ogbonna Esonu, Dhamin Al-Khalili, Come Rozon
   Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS & BiCMOS Circuits. [Citation Graph (0, 0)][DBLP]
   ISCAS, 1993, pp:1714-1717 [Conf]
   
9. Donald Shaw, Dhamin Al-Khalili, Come Rozon
   Deriving accurate ASIC cell fault models for VITAL compliant VHDL simulation. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2001, pp:263-266 [Conf]
   
10. R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili
    Power implications of precision limited arithmetic in floating point FIR filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:165-168 [Conf]
    
11. J. M. P. Langlois, Dhamin Al-Khalili
    Hardware optimized direct digital frequency synthesizer architecture with 60 dBc spectral purity. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:361-364 [Conf]
    
12. R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili
    Energy delay analysis of partial product reduction methods for parallel multiplier implementation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:201-204 [Conf]
    
13. R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili
    Energy delay measures of barrel switch architectures for pre-alignment of floating point operands for addition. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:235-238 [Conf]
    
14. Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili
    Quadratic deferred-merge embedding algorithm for zero skew clock distribution network. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:119-125 [Conf]
    
15. R. V. K. Pillai, Asim J. Al-Khalili, Dhamin Al-Khalili
    A Low Power Floating Point Accumulator. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:330-0 [Conf]
    
16. Hussam Al-Hertani, Dhamin Al-Khalili, Come Rozon
    Leakage power dissipation in UDSM logic gates. [Citation Graph (0, 0)][DBLP]
    Circuits, Signals, and Systems, 2005, pp:132-136 [Conf]
    
17. Michael Gallant, Dhamin Al-Khalili
    Synthesis of low-power CMOS circuits using hybrid topologies. [Citation Graph (0, 0)][DBLP]
    Integration, 1999, v:27, n:2, pp:143-163 [Journal]
    
18. Donald B. Shaw, Dhamin Al-Khalili, Come Rozon
    Fault security analysis of CMOS VLSI circuits using defect-injectable VHDL models. [Citation Graph (0, 0)][DBLP]
    Integration, 2002, v:32, n:1-2, pp:77-97 [Journal]
    
19. Donald Shaw, Dhamin Al-Khalili, Come Rozon
    Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries. [Citation Graph (0, 0)][DBLP]
    Integration, 2006, v:39, n:4, pp:382-406 [Journal]
    
20. Donald B. Shaw, Dhamin Al-Khalili, Come Rozon
    IC Bridge Fault Modeling for IP Blocks Using Neural Network-Based VHDL Saboteurs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:10, pp:1285-1297 [Journal]
    
21. Asim J. Al-Khalili, Yong Zhu, Dhamin Al-Khalili
    A module generator for optimized CMOS buffers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:10, pp:1028-1046 [Journal]
    
22. Adnan Kabbani, Dhamin Al-Khalili, Asim J. Al-Khalili
    Technology-portable analytical model for DSM CMOS inverter transition-time estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1177-1187 [Journal]
    
23. Adnan Kabbani, Dhamin Al-Khalili, Asim J. Al-Khalili
    Delay analysis of CMOS gates using modified logical effort model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:6, pp:937-947 [Journal]
    
24. Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili
    Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:10, pp:1637-1643 [Journal]
    
25. 
    Accurate Total Static Leakage Current Estimation in Transistor Stacks. [Citation Graph (, )][DBLP]
    
    
26. 
    An Optimized Design Approach for Squaring Large Integers Using Embedded Hardwired Multipliers. [Citation Graph (, )][DBLP]
    
    
27. 
    FPGA-Based Efficient Design Approach for Large-Size Two's Complement Squarers. [Citation Graph (, )][DBLP]
    
    
28. 
    Efficient FPGA implementation of complex multipliers using the logarithmic number system. [Citation Graph (, )][DBLP]