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Luca Breveglieri: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Luca Breveglieri, Israel Koren, Paolo Maistri
    Detecting Faults in Four Symmetric Key Block Ciphers. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:258-268 [Conf]
  2. Luca Breveglieri, Luigi Dadda, Vincenzo Piuri
    Fast Arithmetic and Fault Tolerance in the FERMI System. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:374-383 [Conf]
  3. Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri
    On the Propagation of Faults and Their Detection in a Hardware Implementation of the Advanced Encryption Standard. [Citation Graph (0, 0)][DBLP]
    ASAP, 2002, pp:303-0 [Conf]
  4. Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri
    Concurrent Fault Detection in a Hardware Implementation of the RC5 Encryption Algorithm. [Citation Graph (0, 0)][DBLP]
    ASAP, 2003, pp:423-432 [Conf]
  5. Guido Bertoni, Luca Breveglieri, Farina Roberto, Francesco Regazzoni
    Speeding Up AES By Extending a 32 bit Processor Instruction Set. [Citation Graph (0, 0)][DBLP]
    ASAP, 2006, pp:275-282 [Conf]
  6. Luca Breveglieri, Luigi Dadda, Vincenzo Piuri
    Column Compression Pipelined Multipliers. [Citation Graph (0, 0)][DBLP]
    ASAP, 1995, pp:93-103 [Conf]
  7. Luca Breveglieri, Alessandra Cherubini, Marco Macchetti
    On the Generalized Linear Equivalence of Functions Over Finite Fields. [Citation Graph (0, 0)][DBLP]
    ASIACRYPT, 2004, pp:79-91 [Conf]
  8. Guido Bertoni, Luca Breveglieri, Pasqualina Fragneto, Marco Macchetti, Stefano Marchesin
    Efficient Software Implementation of AES on 32-Bit Platforms. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:159-171 [Conf]
  9. Guido Bertoni, Luca Breveglieri, Pasqualina Fragneto
    Efficient finite field digital-serial multiplier architecture for cryptography applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:812- [Conf]
  10. Guido Bertoni, Luca Breveglieri, Pasqualina Fragneto, Gerardo Pelosi, L. Sportiello
    Software implementation of Tate pairing over GF(2m). [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:7-11 [Conf]
  11. Luca Breveglieri, Israel Koren, Paolo Maistri
    Incorporating Error Detection and Online Reconfiguration into a Regular Architecture for the Advanced Encryption Standard. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:72-80 [Conf]
  12. Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri
    An Efficient Hardware-Based Fault Diagnosis Scheme for AES: Performances and Cost. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:130-138 [Conf]
  13. Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri
    A Parity Code Based Fault Detection for an Implementation of the Advanced Encryption Standard. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:51-59 [Conf]
  14. Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri
    Detecting and Locating Faults in VLSI Implementations of the Advanced Encryption Standard. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:105-0 [Conf]
  15. A. Dell'Acqua, M. Hansen, S. Inkinen, B. Lofstedt, J. P. Vanuxem, Christer Svensson, Jiren Yuan, H. Hentzell, L. Del Buono, J. David, J. F. Genat, H. Lebbolo, O. LeDortz, P. Nayman, A. Savoy-Navarro, R. Zitoun, Cesare Alippi, Luca Breveglieri, Luigi Dadda, Vincenzo Piuri, Fabio Salice, Mariagiovanna Sami, Renato Stefanelli, P. Cattaneo, G. Fumagalli, G. Goggi, S. Brigati, Umberto Gatti, Franco Maloberti, Guido Torelli, P. Carlson, A. Kerek, Goran Appelquist, S. Berglund, C. Bohm, Magnus Engström, N. Yamdagni, Rolf Sundblad, I. Höglund, S. T. Persson
    System Level Policies for Fault Tolerance Issues in the FERMI Project. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:1-8 [Conf]
  16. Luca Breveglieri, Alessandra Cherubini, Claudio Citrini, Stefano Crespi-Reghizzi
    Fair First Languages and Parallel Programme Schemes. [Citation Graph (0, 0)][DBLP]
    Developments in Language Theory, 1993, pp:389-418 [Conf]
  17. Luca Breveglieri, Israel Koren
    Workshop on Fault Diagnosis and Tolerance in Cryptography. [Citation Graph (0, 0)][DBLP]
    DSN, 2004, pp:902- [Conf]
  18. Luca Breveglieri, Claudio Citrini, Stefano Crespi-Reghizzi
    Deterministic Dequeue Automata and LL(1) Parsing of Breadth-Depth Grammars. [Citation Graph (0, 0)][DBLP]
    FCT, 1991, pp:146-156 [Conf]
  19. Luca Breveglieri, Stefano Crespi-Reghizzi, Alessandra Cherubini
    Modeling Operating Systems Schedulers with Multi-Stack-Queue Grammars. [Citation Graph (0, 0)][DBLP]
    FCT, 1999, pp:161-172 [Conf]
  20. Luca Breveglieri, Israel Koren, Paolo Maistri, M. Ravasio
    Incorporating Error Detection in an RSA Architecture. [Citation Graph (0, 0)][DBLP]
    FDTC, 2006, pp:71-79 [Conf]
  21. Luca Breveglieri, Israel Koren, Paolo Maistri
    A Fault Attack Against the FOX Cipher Family. [Citation Graph (0, 0)][DBLP]
    FDTC, 2006, pp:98-105 [Conf]
  22. Luca Breveglieri, Alessandra Cherubini, Stefano Crespi-Reghizzi
    Real-Time Scheduling by Queue Automata. [Citation Graph (0, 0)][DBLP]
    FTRTFT, 1992, pp:131-147 [Conf]
  23. Thomas J. Wollinger, Guido Bertoni, Luca Breveglieri, Christof Paar
    Performance of HECC Coprocessors Using Inversion-Free Formulae. [Citation Graph (0, 0)][DBLP]
    ICCSA (3), 2006, pp:1004-1012 [Conf]
  24. Marco Macchetti, Mario Caironi, Luca Breveglieri, Alessandra Cherubini
    A Complete Formulation of Generalized Affine Equivalence. [Citation Graph (0, 0)][DBLP]
    ICTCS, 2005, pp:338-347 [Conf]
  25. Régis Leveugle, Yervant Zorian, Luca Breveglieri, André K. Nieuwland, Klaus Rothbart, Jean-Pierre Seifert
    On-Line Testing for Secure Implementations: Design and Validation. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:211- [Conf]
  26. Luca Breveglieri, Paolo Maistri, Israel Koren
    A Note on Error Detection in an RSA Architecture by Means of Residue Codes. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:176-177 [Conf]
  27. Guido Bertoni, A. Bircan, Luca Breveglieri, Pasqualina Fragneto, Marco Macchetti, Vittorio Zaccaria
    About the performances of the Advanced Encryption Standard in embedded systems with cache memory. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:145-148 [Conf]
  28. Guido Bertoni, Luca Breveglieri, Thomas J. Wollinger, Christof Paar
    Finding Optimum Parallel Coprocessor Design for Genus 2 Hyperelliptic Curve Cryptosystems. [Citation Graph (0, 0)][DBLP]
    ITCC (2), 2004, pp:538-0 [Conf]
  29. Guido Bertoni, Vittorio Zaccaria, Luca Breveglieri, Matteo Monchiero, Gianluca Palermo
    AES Power Attack Based on Induced Cache Miss and Countermeasure. [Citation Graph (0, 0)][DBLP]
    ITCC (1), 2005, pp:586-591 [Conf]
  30. Fabio Sozzani, Guido Bertoni, Stefano Turcato, Luca Breveglieri
    A Parallelized Design for an Elliptic Curve Cryptosystem Coprocessor. [Citation Graph (0, 0)][DBLP]
    ITCC (1), 2005, pp:626-630 [Conf]
  31. Guido Bertoni, Luca Breveglieri, Pasqualina Fragneto, Gerardo Pelosi
    Parallel Hardware Architectures for the Cryptographic Tate Pairing. [Citation Graph (0, 0)][DBLP]
    ITNG, 2006, pp:186-191 [Conf]
  32. Guido Bertoni, Luca Breveglieri, Matteo Venturi
    ECC Hardware Coprocessors for 8-bit Systems and Power Consumption Considerations. [Citation Graph (0, 0)][DBLP]
    ITNG, 2006, pp:573-574 [Conf]
  33. Giovanni Agosta, Luca Breveglieri, Gerardo Pelosi, Martino Sykora
    Programming Highly Parallel Reconfigurable Architectures for Public-Key Cryptographic Applications. [Citation Graph (0, 0)][DBLP]
    ITNG, 2007, pp:3-10 [Conf]
  34. Luca Breveglieri, Alessandra Cherubini, Stefano Crespi-Reghizzi
    Deterministic Parsing for Augmented Context-free Grammars. [Citation Graph (0, 0)][DBLP]
    MFCS, 1995, pp:326-336 [Conf]
  35. Guido Bertoni, Luca Breveglieri, Matteo Venturi
    Power Aware Design of an Elliptic Curve Coprocessor for 8 bit Platforms. [Citation Graph (0, 0)][DBLP]
    PerCom Workshops, 2006, pp:337-341 [Conf]
  36. Kubilay Atasu, Luca Breveglieri, Marco Macchetti
    Efficient AES implementations for ARM based platforms. [Citation Graph (0, 0)][DBLP]
    SAC, 2004, pp:841-845 [Conf]
  37. Anna Antola, Alberto Avai, Luca Breveglieri, Andrea Paparella
    Modular Design Methodologies for Image Processing Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:260-263 [Conf]
  38. Luca Breveglieri, Alessandra Cherubini, Claudio Citrini, Stefano Crespi-Reghizzi
    Multi-Push-Down Languages and Grammars. [Citation Graph (0, 0)][DBLP]
    Int. J. Found. Comput. Sci., 1996, v:7, n:3, pp:253-292 [Journal]
  39. Luca Breveglieri
    Fair Expressions and Regular Languages over Lists. [Citation Graph (0, 0)][DBLP]
    ITA, 1997, v:31, n:1, pp:15-66 [Journal]
  40. Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri
    Error Analysis and Detection Procedures for a Hardware Implementation of the Advanced Encryption Standard. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:4, pp:492-505 [Journal]
  41. Luca Breveglieri, Israel Koren
    Guest Editors' Introduction: Special Section on Fault Diagnosis and Tolerance in Cryptography. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:9, pp:1073-1074 [Journal]
  42. Luca Breveglieri, Israel Koren, Paolo Maistri
    An Operation-Centered Approach to Fault Detection in Symmetric Cryptography Ciphers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:5, pp:635-649 [Journal]
  43. Anna Antola, Alberto Avai, Luca Breveglieri
    Modular design methodologies for image processing architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:4, pp:408-414 [Journal]
  44. Luca Breveglieri, Luigi Dadda
    A VLSI inner product macrocell. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:292-298 [Journal]

  45. Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits. [Citation Graph (, )][DBLP]


  46. Can Knowledge Regarding the Presence of Countermeasures Against Fault Attacks Simplify Power Attacks on Cryptographic Devices?. [Citation Graph (, )][DBLP]


  47. Countermeasures against Branch Target Buffer Attacks. [Citation Graph (, )][DBLP]


  48. A FPGA Coprocessor for the Cryptographic Tate Pairing over Fp. [Citation Graph (, )][DBLP]


  49. Practical Power Analysis Attacks to RSA on a Large IP Portfolio SoC. [Citation Graph (, )][DBLP]


  50. A 640 Mbit/S 32-Bit Pipelined Implementation of the AES Algorithm. [Citation Graph (, )][DBLP]


  51. Alphabetical Satisfiability Problem for Trace Equations. [Citation Graph (, )][DBLP]


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