The SCEAS System
Navigation Menu

Search the dblp DataBase


Luigi Raffo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Danilo Pani, Luigi Raffo
    A VLSI Multiplication-and-Add Scheme Based on Swarm Intelligence Approaches. [Citation Graph (0, 0)][DBLP]
    ANTS Workshop, 2004, pp:13-24 [Conf]
  2. Gianmarco Angius, Cristian Manca, Danilo Pani, Luigi Raffo
    Cooperative VLSI Tiled Architectures: Stigmergy in a Swarm Coprocessor. [Citation Graph (0, 0)][DBLP]
    ANTS Workshop, 2006, pp:396-403 [Conf]
  3. Federico Angiolini, Paolo Meloni, Salvatore Carta, Luca Benini, Luigi Raffo
    Contrasting a NoC and a traditional interconnect fabric with layout awareness. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:124-129 [Conf]
  4. Stergios Stergiou, Federico Angiolini, Salvatore Carta, Luigi Raffo, Davide Bertozzi, Giovanni De Micheli
    ast pipes Lite: A Synthesis Oriented Design Library For Networks on Chips. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1188-1193 [Conf]
  5. Danilo Pani, Giuseppe Passino, Luigi Raffo
    Run-time Adaptive Resources Allocation and Balancing on Nanoprocessors Arrays. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:492-499 [Conf]
  6. Giovanni Busonera, Salvatore Carta, Andrea Marongiu, Luigi Raffo
    Automatic Application Partitioning on FPGA/CPU Systems Based on Detailed Low-Level Information. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:265-268 [Conf]
  7. Giacomo M. Bisio, Gian Marco Bo, M. Confalone, Luigi Raffo, Silvio P. Sabatini, M. P. Zizola
    An Analog VLSI Computational Engine for Early Vision Tasks. [Citation Graph (0, 0)][DBLP]
    ICANN, 1997, pp:1175-1180 [Conf]
  8. Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo
    Designing application-specific networks on chips with floorplan information. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:355-362 [Conf]
  9. Andrea Alimonda, Salvatore Carta, Luigi Raffo
    A modular digital VLSI architecture for stereo depth estimation in industrial applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:481-484 [Conf]
  10. Silvio Bolliri, Paolo Porcu, Luigi Raffo
    A micro-power mixed signal IC for battery-operated burglar alarm systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:73-77 [Conf]
  11. Federico Angiolini, Paolo Meloni, Luca Benini, Salvatore Carta, Luigi Raffo
    Networks on Chips: A Synthesis Perspective. [Citation Graph (0, 0)][DBLP]
    PARCO, 2005, pp:745-752 [Conf]
  12. Danilo Pani, Luigi Raffo
    A Swarm Intelligence Based VLSI Multiplication-and-Add Scheme. [Citation Graph (0, 0)][DBLP]
    PPSN, 2004, pp:362-371 [Conf]
  13. Giacomo Indiveri, Luigi Raffo, Silvio P. Sabatini, Giacomo M. Bisio
    A recurrent neural architecture mimicking cortical preattentive vision systems. [Citation Graph (0, 0)][DBLP]
    Neurocomputing, 1996, v:11, n:2-4, pp:155-170 [Journal]
  14. Danilo Pani, Luigi Raffo
    Stigmergic approaches applied to flexible fault-tolerant digital VLSI architectures. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2006, v:66, n:8, pp:1014-1024 [Journal]
  15. Bruno Crespi, Alex Cozzi, Luigi Raffo, Silvio P. Sabatini
    Analog computation for phase-based disparity estimation: continuous and discrete models. [Citation Graph (0, 0)][DBLP]
    Mach. Vis. Appl., 1998, v:11, n:2, pp:83-95 [Journal]
  16. Silvio P. Sabatini, Luigi Raffo, Giacomo M. Bisio
    Functional Periodic Intracortical Couplings Induced by Structured Lateral Inhibition in a Linear Cortical Network. [Citation Graph (0, 0)][DBLP]
    Neural Computation, 1997, v:9, n:3, pp:525-531 [Journal]
  17. Maurizio Valle, Luigi Raffo, Daniele D. Caviglia, Giacomo M. Bisio
    A VLSI Image Processing Architecture Dedicated to Real-Time Quality Control Analysis in an Industrial Plant. [Citation Graph (0, 0)][DBLP]
    Real-Time Imaging, 1996, v:2, n:6, pp:361-371 [Journal]
  18. Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo
    Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:158-163 [Conf]
  19. Antonio Pullini, Federico Angiolini, Paolo Meloni, David Atienza, Srinivasan Murali, Luigi Raffo, Giovanni De Micheli, Luca Benini
    NoC Design and Implementation in 65nm Technology. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:273-282 [Conf]
  20. Srinivasan Murali, David Atienza, Paolo Meloni, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo
    Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:869-880 [Journal]
  21. Luigi Raffo, Silvio P. Sabatini, M. Mantelli, A. De Gloria, Giacomo M. Bisio
    Design of an ASIP architecture for low-level visual elaborations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:145-153 [Journal]
  22. Salvatore Carta, Danilo Pani, Luigi Raffo
    Reconfigurable Coprocessor for Multimedia Application Domain. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:44, n:1-2, pp:135-152 [Journal]

  23. Self organization on a swarm computing fabric: a new way to look at fault tolerance. [Citation Graph (, )][DBLP]

  24. On the impact of serialization on the cache performances in Network-on-Chip based MPSoCs. [Citation Graph (, )][DBLP]

  25. A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode Switching. [Citation Graph (, )][DBLP]

  26. Pre-placement of VLSI blocks through learning neural networks. [Citation Graph (, )][DBLP]

  27. Exploiting FPGAs for technology-aware system-level evaluation of multi-core architectures. [Citation Graph (, )][DBLP]

  28. A Novel Non-exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs. [Citation Graph (, )][DBLP]

  29. Impact of Half-Duplex and Full-Duplex DMA Implementations on NoC Performance. [Citation Graph (, )][DBLP]

  30. A DVB-T Based System for the Diffusion of Tele-Home Care Practice. [Citation Graph (, )][DBLP]

  31. Non-Invasive Real-Time Fetal ECG Extraction - A Block-on-Line DSP Implementation based on the JADE Algorithm. [Citation Graph (, )][DBLP]

Search in 0.018secs, Finished in 0.020secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002