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Srinivasan Murali: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Srinivasan Murali, Luca Benini, Giovanni De Micheli
    Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:27-32 [Conf]
  2. Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli
    Mapping and configuration methods for multi-use-case networks on chips. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:146-151 [Conf]
  3. Rutuparna Tamhankar, Srinivasan Murali, Giovanni De Micheli
    Performance driven reliable link design for networks on chips. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:749-754 [Conf]
  4. Martijn Coenen, Srinivasan Murali, Andrei Radulescu, Kees Goossens, Giovanni De Micheli
    A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:130-135 [Conf]
  5. Srinivasan Murali, David Atienza, Luca Benini, Giovanni De Micheli
    A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:845-848 [Conf]
  6. Srinivasan Murali, Giovanni De Micheli
    SUNMAP: a tool for automatic topology selection and generation for NoCs. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:914-919 [Conf]
  7. Antoine Jalabert, Srinivasan Murali, Luca Benini, Giovanni De Micheli
    ×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:884-889 [Conf]
  8. Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli
    A methodology for mapping multiple use-cases onto networks on chips. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:118-123 [Conf]
  9. Srinivasan Murali, Giovanni De Micheli
    Bandwidth-Constrained Mapping of Cores onto NoC Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:896-903 [Conf]
  10. Srinivasan Murali, Giovanni De Micheli
    An Application-Specific Design Methodology for STbus Crossbar Generation. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1176-1181 [Conf]
  11. Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo
    Designing application-specific networks on chips with floorplan information. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:355-362 [Conf]
  12. Srinivasan Murali, Theo Theocharides, Narayanan Vijaykrishnan, Mary Jane Irwin, Luca Benini, Giovanni De Micheli
    Analysis of Error Recovery Schemes for Networks on Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:434-442 [Journal]
  13. Davide Bertozzi, Antoine Jalabert, Srinivasan Murali, Rutuparna Tamhankar, Stergios Stergiou, Luca Benini, Giovanni De Micheli
    NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2005, v:16, n:2, pp:113-129 [Journal]
  14. Ilhan Hatirnaz, Stéphane Badel, Nuria Pazos, Yusuf Leblebici, Srinivasan Murali, David Atienza, Giovanni De Micheli
    Early wire characterization for predictable network-on-chip global interconnects. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:57-64 [Conf]
  15. Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo
    Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:158-163 [Conf]
  16. Antonio Pullini, Federico Angiolini, Paolo Meloni, David Atienza, Srinivasan Murali, Luigi Raffo, Giovanni De Micheli, Luca Benini
    NoC Design and Implementation in 65nm Technology. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:273-282 [Conf]
  17. Srinivasan Murali, Giovanni De Micheli
    An Application-Specific Design Methodology for STbus Crossbar Generation [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  18. Antonio Pullini, Federico Angiolini, Srinivasan Murali, David Atienza, Giovanni De Micheli, Luca Benini
    Bringing NoCs to 65 nm. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:5, pp:75-85 [Journal]
  19. Srinivasan Murali, David Atienza, Paolo Meloni, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo
    Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:869-880 [Journal]

  20. Synthesis of networks on chips for 3D systems on chips. [Citation Graph (, )][DBLP]


  21. Temperature-aware processor frequency assignment for MPSoCs using convex optimization. [Citation Graph (, )][DBLP]


  22. Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems. [Citation Graph (, )][DBLP]


  23. NoC topology synthesis for supporting shutdown of voltage islands in SoCs. [Citation Graph (, )][DBLP]


  24. Networks on Chips: from research to products. [Citation Graph (, )][DBLP]


  25. Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization. [Citation Graph (, )][DBLP]


  26. SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips. [Citation Graph (, )][DBLP]


  27. A method to remove deadlocks in Networks-on-Chips with Wormhole flow control. [Citation Graph (, )][DBLP]


  28. A method for calculating hard QoS guarantees for Networks-on-Chip. [Citation Graph (, )][DBLP]


  29. Reliability Support for On-Chip Memories Using Networks-on-Chip. [Citation Graph (, )][DBLP]


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