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H. Peter Hofstee: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kevin J. Nowka, H. Peter Hofstee
    Circuits and Microarchitecture for Gigahertz VLSI Designs. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1997, pp:284-287 [Conf]
  2. Dac Pham, Hans-Werner Anderson, Erwin Behnen, Mark Bolliger, Sanjay Gupta, H. Peter Hofstee, Paul Harvey, Charles R. Johns, James A. Kahle, Atsushi Kameyama, John M. Keaty, Bob Le, Sang Lee, Tuyen V. Nguyen, John G. Petrovick, Mydung Pham, Juergen Pille, Stephen D. Posluszny, Mack Riley, Joseph Verock, James D. Warnock, Steve Weitzel, Dieter F. Wendel
    Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:871-878 [Conf]
  3. Wendy Belluomini, Chris J. Myers, H. Peter Hofstee
    Verification of Delayed-Reset Domino Circuits Using ATACS. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1999, pp:3-12 [Conf]
  4. H. Peter Hofstee, Michael N. Day
    Hardware and software architectures for the CELL processor. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:1- [Conf]
  5. Stephen D. Posluszny, N. Aoki, D. Boerstler, P. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, N. Kojima, Ohsang Kwon, K. Lee, D. Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia
    "Timing closure by design, " a high frequency microprocessor design methodology. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:712-717 [Conf]
  6. H. Peter Hofstee, Johan J. Lukkien, Jan L. A. van de Snepscheut
    A Distributed Implementation of a Task Pool. [Citation Graph (0, 0)][DBLP]
    Research Directions in High-Level Parallel Programming Languages, 1991, pp:338-348 [Conf]
  7. H. Peter Hofstee
    Power Efficient Processor Architecture and The Cell Processor. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:258-262 [Conf]
  8. H. Peter Hofstee
    Power-Constrained Microprocessor Design. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:14-16 [Conf]
  9. H. Peter Hofstee
    Distributing a Class of Sequential Programs. [Citation Graph (0, 0)][DBLP]
    MPC, 1992, pp:139-162 [Conf]
  10. H. Peter Hofstee
    Invited speakers II - Real-time supercomputing and technology for games and entertainment. [Citation Graph (0, 0)][DBLP]
    SC, 2006, pp:199- [Conf]
  11. David Heidel, Sang H. Dhong, H. Peter Hofstee, Michael Immediato, Kevin J. Nowka, Joel Silberman, Kevin Stawiasz
    High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:234-238 [Conf]
  12. David H. Allen, Sang H. Dhong, H. Peter Hofstee, Jens Leenstra, Kevin J. Nowka, Daniel L. Stasiak, Dieter F. Wendel
    Custom circuit design as a driver of microprocessor performance. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2000, v:44, n:6, pp:799-822 [Journal]
  13. James A. Kahle, Michael N. Day, H. Peter Hofstee, Charles R. Johns, Theodore R. Maeurer, David Shippy
    Introduction to the Cell multiprocessor. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2005, v:49, n:4-5, pp:589-604 [Journal]
  14. H. Peter Hofstee, Jun Sawada
    Derivation of a rotator circuit with homogeneous interconnect. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 2001, v:77, n:2-4, pp:131-135 [Journal]
  15. Michael Gschwind, H. Peter Hofstee, Brian K. Flachs, Martin Hopkins, Yukio Watanabe, Takeshi Yamazaki
    Synergistic Processing in Cell's Multicore Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:2, pp:10-24 [Journal]
  16. H. Peter Hofstee
    Distributing a Class of Sequential Programs. [Citation Graph (0, 0)][DBLP]
    Sci. Comput. Program., 1994, v:22, n:1-2, pp:45-65 [Journal]
  17. H. Peter Hofstee, Alain J. Martin, Jan L. A. van de Snepscheut
    Distributed Sorting. [Citation Graph (0, 0)][DBLP]
    Sci. Comput. Program., 1990, v:15, n:2-3, pp:119-133 [Journal]
  18. Wendy Belluomini, Chris J. Myers, H. Peter Hofstee
    Timed circuit verification using TEL structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:129-146 [Journal]

  19. Communication and Synchronization in the Cell Processor - Invited Talk. [Citation Graph (, )][DBLP]

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