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Michael Gschwind :
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Alexandre E. Eichenberger , Kathryn M. O'Brien , Kevin O'Brien , Peng Wu , Tong Chen , Peter H. Oden , Daniel A. Prener , Janice C. Shepherd , Byoungro So , Zehra Sura , Amy Wang , Tao Zhang , Peng Zhao , Michael Gschwind Optimizing Compiler for the CELL Processor. [Citation Graph (0, 0)][DBLP ] IEEE PACT, 2005, pp:161-172 [Conf ] Michael Gschwind , Erik R. Altman Precise Exception Semantics in Dynamic Compilation. [Citation Graph (0, 0)][DBLP ] CC, 2002, pp:95-110 [Conf ] Michael Gschwind Chip multiprocessing and the cell broadband engine. [Citation Graph (0, 0)][DBLP ] Conf. Computing Frontiers, 2006, pp:1-8 [Conf ] Valentina Salapura , Randy Bickford , Matthias A. Blumrich , Arthur A. Bright , Dong Chen , Paul Coteus , Alan Gara , Mark Giampapa , Michael Gschwind , Manish Gupta , Shawn Hall , Ruud A. Haring , Philip Heidelberger , Dirk Hoenicke , Gerard V. Kopcsay , Martin Ohmacht , Rick A. Rand , Todd Takken , Pavlos Vranas Power and performance optimization at the system level. [Citation Graph (0, 0)][DBLP ] Conf. Computing Frontiers, 2005, pp:125-132 [Conf ] Michael Gschwind Instruction set selection for ASIP design. [Citation Graph (0, 0)][DBLP ] CODES, 1999, pp:7-11 [Conf ] Valentina Salapura , Michael Gschwind Hardware/Software Co-Design of a Fuzzy RISC Processor. [Citation Graph (0, 0)][DBLP ] DATE, 1998, pp:875-882 [Conf ] Kemal Ebcioglu , Erik R. Altman , Sumedh W. Sathaye , Michael Gschwind Execution-Based Scheduling for VLIW Architectures. [Citation Graph (0, 0)][DBLP ] Euro-Par, 1999, pp:1269-1280 [Conf ] Michael Gschwind , Christian Mautner The Design of a Stack-Based Microprocessor. [Citation Graph (0, 0)][DBLP ] FPL, 1994, pp:326-331 [Conf ] Michael Gschwind , Christian Mautner Migration from Schematic-Based Designs to a VHDL Synthesis Environment. [Citation Graph (0, 0)][DBLP ] FPL, 1996, pp:346-355 [Conf ] Michael Gschwind , Valentina Salapura A VHDL Design Methodology for FPGAs. [Citation Graph (0, 0)][DBLP ] FPL, 1995, pp:208-217 [Conf ] Valentina Salapura , Michael Gschwind , Oliver Maischberger A Fast FPGA Implementation of a General Purpose Neuron. [Citation Graph (0, 0)][DBLP ] FPL, 1994, pp:175-182 [Conf ] Michael Gschwind , Kemal Ebcioglu , Erik R. Altman , Sumedh W. Sathaye Binary translation and architecture convergence issues for IBM system/390. [Citation Graph (0, 0)][DBLP ] ICS, 2000, pp:336-347 [Conf ] Kemal Ebcioglu , Erik R. Altman , Sumedh W. Sathaye , Michael Gschwind Optimizations and Oracle Parallelism with Dynamic Translation. [Citation Graph (0, 0)][DBLP ] MICRO, 1999, pp:284-0 [Conf ] Viji Srinivasan , David Brooks , Michael Gschwind , Pradip Bose , Victor V. Zyuban , Philip N. Strenski , Philip G. Emma Optimizing pipelines for power and performance. [Citation Graph (0, 0)][DBLP ] MICRO, 2002, pp:333-344 [Conf ] Pradip Bose , David Brooks , Alper Buyuktosunoglu , Peter W. Cook , K. Das , Philip G. Emma , Michael Gschwind , Hans M. Jacobson , Tejas Karkhanis , Prabhakar Kudva , Stanley Schuster , James E. Smith , Viji Srinivasan , Victor V. Zyuban , David H. Albonesi , Sandhya Dwarkadas Early-Stage Definition of LPX: A Low Power Issue-Execute Processor. [Citation Graph (0, 0)][DBLP ] PACS, 2002, pp:1-17 [Conf ] Michael Gschwind Reprogrammable hardware for educational purposes. [Citation Graph (0, 0)][DBLP ] SIGCSE, 1994, pp:183-187 [Conf ] Michael Gschwind , Erik R. Altman , Sumedh W. Sathaye , Paul Ledak , David Appenzeller Dynamic and Transparent Binary Translation. [Citation Graph (0, 0)][DBLP ] IEEE Computer, 2000, v:33, n:3, pp:54-59 [Journal ] David Brooks , Pradip Bose , Viji Srinivasan , Michael Gschwind , Philip G. Emma , Michael G. Rosenfield New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors. [Citation Graph (0, 0)][DBLP ] IBM Journal of Research and Development, 2003, v:47, n:5-6, pp:653-670 [Journal ] Alexandre E. Eichenberger , Kevin O'Brien , Kathryn M. O'Brien , Peng Wu , Tong Chen , Peter H. Oden , Daniel A. Prener , Janice C. Shepherd , Byoungro So , Zehra Sura , Amy Wang , Tao Zhang , Peng Zhao , Michael Gschwind , Roch Archambault , Yaoqing Gao , Roland Koo Using advanced compiler technology to exploit the performance of the Cell Broadband EngineTM architecture. [Citation Graph (0, 0)][DBLP ] IBM Systems Journal, 2006, v:45, n:1, pp:59-84 [Journal ] Michael Gschwind , H. Peter Hofstee , Brian K. Flachs , Martin Hopkins , Yukio Watanabe , Takeshi Yamazaki Synergistic Processing in Cell's Multicore Architecture. [Citation Graph (0, 0)][DBLP ] IEEE Micro, 2006, v:26, n:2, pp:10-24 [Journal ] Michael Gschwind , Erik R. Altman Optimization and precise exceptions in dynamic compilation. [Citation Graph (0, 0)][DBLP ] SIGARCH Computer Architecture News, 2001, v:29, n:1, pp:66-74 [Journal ] Michael Gschwind FTP Access As a User-defined File System. [Citation Graph (0, 0)][DBLP ] Operating Systems Review, 1994, v:28, n:2, pp:73-80 [Journal ] Kemal Ebcioglu , Erik R. Altman , Michael Gschwind , Sumedh W. Sathaye Dynamic Binary Translation and Optimization. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 2001, v:50, n:6, pp:529-548 [Journal ] Victor V. Zyuban , David Brooks , Viji Srinivasan , Michael Gschwind , Pradip Bose , Philip N. Strenski , Philip G. Emma Integrated Analysis of Power and Performance for Pipelined Microprocessors. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 2004, v:53, n:8, pp:1004-1016 [Journal ] Michael Gschwind The Cell Broadband Engine: Exploiting Multiple Levels of Parallelism in a Chip Multiprocessor. [Citation Graph (0, 0)][DBLP ] International Journal of Parallel Programming, 2007, v:35, n:3, pp:233-262 [Journal ] Michael Gschwind , Valentina Salapura , D. Maurer FPGA prototyping of a RISC processor core for embedded applications. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:241-250 [Journal ] Optimizing data sharing and address translation for the Cell BE Heterogeneous Chip Multiprocessor. [Citation Graph (, )][DBLP ] Next-Generation Performance Counters: Towards Monitoring Over Thousand Concurrent Events. [Citation Graph (, )][DBLP ] Cell GC: using the cell synergistic processor as a garbage collection coprocessor. [Citation Graph (, )][DBLP ] An Open Source Environment for Cell Broadband Engine System Software. [Citation Graph (, )][DBLP ] Application Acceleration with the Cell Broadband Engine. [Citation Graph (, )][DBLP ] Search in 0.028secs, Finished in 0.029secs