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Mitchell A. Thornton: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Lun Li, Alex Fit-Florea, Mitchell A. Thornton, David W. Matula
    Performance Evaluation of a Novel Direct Table Lookup Method and Architecture with Application to 16-bit Integer Functions. [Citation Graph (0, 0)][DBLP]
    ASAP, 2006, pp:99-104 [Conf]
  2. Per Lindgren, Mikael Kerttu, Mitchell A. Thornton, Rolf Drechsler
    Low power optimization technique for BDD mapped circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:615-621 [Conf]
  3. Robert B. Reese, Mitchell A. Thornton, Cherrice Traver
    A Coarse-Grain Phased Logic CPU. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:2-13 [Conf]
  4. Kenneth Fazel, Mitchell A. Thornton, Robert B. Reese
    PLFire: A Visualization Tool for Asynchronous Phased Logic Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11096-11097 [Conf]
  5. Mitchell A. Thornton, Rolf Drechsler
    Spectral decision diagrams using graph transformations. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:713-719 [Conf]
  6. Mitchell A. Thornton, Kenneth Fazel, Robert B. Reese, Cherrice Traver
    Generalized Early Evaluation in Self-Timed Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:255-259 [Conf]
  7. Mitchell A. Thornton, J. P. Williams, Rolf Drechsler, Nicole Drechsler
    Variable Reordering for Shared Binary Decision Diagrams Using Output Probabilities. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:758-759 [Conf]
  8. Kenneth Fazel, Lun Li, Mitchell A. Thornton, Robert B. Reese, Cherrice Traver
    Performance enhancement in phased logic circuits using automatic slack-matching buffer insertion. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:413-416 [Conf]
  9. Lun Li, Mitchell A. Thornton, David W. Matula
    A digit serial algorithm for the integer power operation. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:302-307 [Conf]
  10. Whitney J. Townsend, Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller
    Computing walsh, arithmetic, and reed-muller spectral decision diagrams using graph transformations. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:178-183 [Conf]
  11. Mitchell A. Thornton, D. L. Andrews
    Graph Analysis and Transformation Techniques for Runtime Minimization in Multi-Threaded Architectures. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1997, pp:566-575 [Conf]
  12. Robert B. Reese, Mitchell A. Thornton, Cherrice Traver
    Arithmetic Logic Circuits Using Self-Timed Bit Level Dataflow and Early Evaluation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:18-23 [Conf]
  13. Ralph Marczynski, Mitchell A. Thornton, Stephen A. Szygenda
    Test vector generation and classification using FSM traversals. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:309-312 [Conf]
  14. Mikael Kerttu, Per Lindgren, Mitchell A. Thornton, Rolf Drechsler
    Switching activity estimation of finite state machines for low power synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:65-68 [Conf]
  15. Rolf Drechsler, Mitchell A. Thornton
    Computation of Spectral Information from Logic Netlists. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:53-58 [Conf]
  16. Rolf Drechsler, Mitchell A. Thornton, David Wessels
    MDD-Based Synthesis of Multi-Valued Logic Networks. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:41-46 [Conf]
  17. Lun Li, Mitchell A. Thornton, Marek A. Perkowski
    A Quantum CAD Accelerator Based on Grover's Algorithm for Finding the Minimum Fixed Polarity Reed-Muller Form. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:33- [Conf]
  18. D. Michael Miller, Mitchell A. Thornton
    QMDD: A Decision Diagram Structure for Reversible and Quantum Circuits. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:30- [Conf]
  19. Mitchell A. Thornton
    Spectral Transforms of Mixed-radix MVL Functions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2003, pp:329-333 [Conf]
  20. Mitchell A. Thornton
    The Karhunen-Loève Transform of Discrete MVL Functions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2005, pp:194-199 [Conf]
  21. Mitchell A. Thornton, Rolf Drechsler, Wolfgang Günther
    A Method for Approximate Equivalence Checking. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:447-452 [Conf]
  22. Mitchell A. Thornton, D. Michael Miller, Whitney J. Townsend
    Chrestenson Spectrum Computation Using Cayley Color Graphs. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:123-129 [Conf]
  23. J. W. Bruce, Mitchell A. Thornton, L. Shivakumaraiah, P. S. Kokate, X. Li
    Efficient Adder Circuits Based on a Conservative Reversible Logic Gate. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2002, pp:83-88 [Conf]
  24. Lun Li, Alex Fit-Florea, Mitchell A. Thornton, David W. Matula
    Hardware Implementation of an Additive Bit-Serial Algorithm for the Discrete Logarithm Modulo 2k. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:130-135 [Conf]
  25. Lun Li, Mitchell A. Thornton, Stephen A. Szygenda
    A Genetic Approach for Conjunction Scheduling in Symbolic Equivalence Checking. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:32-38 [Conf]
  26. Robert B. Reese, Mitchell A. Thornton, Cherrice Traver
    A Fine-Grain Phased Logic CPU. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:70-79 [Conf]
  27. Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller
    Multi-Output Timed Shannon Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2002, pp:47-52 [Conf]
  28. Frank P. Coyle, Mitchell A. Thornton
    A Framework and Process for Curricular Integration and Innovation Using Project Based Interdisciplinary Teams. [Citation Graph (0, 0)][DBLP]
    ITCC (1), 2005, pp:432-435 [Conf]
  29. Mikael Kerttu, Per Lindgren, Rolf Drechsler, Mitchell A. Thornton
    Low Power Optimization Techniques for BDD Mapped Finite State Machines. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:143-148 [Conf]
  30. Whitney J. Townsend, Mitchell A. Thornton, Parag K. Lala
    On-line Error Detection in a Carry-free Adder. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:251-254 [Conf]
  31. Q. G. Samdani, Mitchell A. Thornton
    Cache Resident Data Locality Analysis. [Citation Graph (0, 0)][DBLP]
    MASCOTS, 2000, pp:539-0 [Conf]
  32. A. Zuzek, Rolf Drechsler, Mitchell A. Thornton
    Boolean function representation and spectral characterization using AND/OR graphs. [Citation Graph (0, 0)][DBLP]
    Integration, 2000, v:29, n:2, pp:101-116 [Journal]
  33. Mitchell A. Thornton
    Performance Evaluation of a Parallel Decoupled Data Driven Multiprocessor. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 2003, v:13, n:3, pp:497-507 [Journal]
  34. Robert B. Reese, Mitchell A. Thornton, Cherrice Traver
    A Coarse-Grain Phased Logic CPU. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:7, pp:788-799 [Journal]
  35. Mitchell A. Thornton
    Signed Binary Addition Circuitry with Inherent Even Parity Outputs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:7, pp:811-816 [Journal]
  36. Robert B. Reese, Mitchell A. Thornton, Cherrice Traver, David Hemmendinger
    Early evaluation for performance enhancement in phased logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:532-550 [Journal]
  37. Mitchell A. Thornton, V. S. S. Nair
    Efficient calculation of spectral coefficients and their applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:11, pp:1328-1341 [Journal]
  38. Mitchell A. Thornton, V. S. S. Nair
    Behavioral synthesis of combinational logic using spectral-based heuristics. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1999, v:4, n:2, pp:219-230 [Journal]

  39. A Low Power High Performance Radix-4 Approximate Squaring Circuit. [Citation Graph (, )][DBLP]


  40. Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits. [Citation Graph (, )][DBLP]


  41. Advances in Quantum Computing Fault Tolerance and Testing. [Citation Graph (, )][DBLP]


  42. Variable Reordering and Sifting for QMDD. [Citation Graph (, )][DBLP]


  43. Quantum Logic Implementation of Unary Arithmetic Operations. [Citation Graph (, )][DBLP]


  44. On the Data Structure Metrics of Quantum Multiple-Valued Decision Diagrams. [Citation Graph (, )][DBLP]


  45. Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL. [Citation Graph (, )][DBLP]


  46. On the Guidance of Reversible Logic Synthesis by Dynamic Variable Reordering. [Citation Graph (, )][DBLP]


  47. Quaternary Addition Circuits Based on SUSLOC Voltage-Mode Cells and Modeling with SystemVerilog©. [Citation Graph (, )][DBLP]


  48. Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits. [Citation Graph (, )][DBLP]


  49. Components and Analysis of Disaster Tolerant Computing. [Citation Graph (, )][DBLP]


  50. Automatic High Level Assertion Generation and Synthesis for Embedded System Design. [Citation Graph (, )][DBLP]


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