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Gordon J. Brebner: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Gordon J. Brebner, Philip James-Roxby, Eric Keller, Chidamber Kulkarni
    Hyper-Programmable Architectures for Adaptable Networked Systems. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:328-338 [Conf]
  2. Gordon J. Brebner, Rob Pooley
    ECOLE: A Configurable Environment for a Local Optical Network of Workstations. [Citation Graph (0, 0)][DBLP]
    CANPC, 1998, pp:45-58 [Conf]
  3. Chidamber Kulkarni, Gordon J. Brebner, Graham Schelle
    Mapping a domain specific language to a platform FPGA. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:924-927 [Conf]
  4. Chidamber Kulkarni, Gordon J. Brebner
    Memory centric thread synchronization on platform FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:959-964 [Conf]
  5. Gordon J. Brebner
    Eccentric SoC Architectures as the Future Norm. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:2-9 [Conf]
  6. Gordon J. Brebner
    Single-Chip Gigabit Mixed-Version IP Router on Virtex-II Pro. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:35-44 [Conf]
  7. Gordon J. Brebner
    The swappable logic unit: a paradigm for virtual hardware. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:77-86 [Conf]
  8. Gordon J. Brebner
    Circlets: Circuits as Applets. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:300-301 [Conf]
  9. Philip James-Roxby, Gordon J. Brebner, Dennis Bemmann
    Time-Critical Software Deceleration in an FCCM. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:3-12 [Conf]
  10. Todd S. Sproull, Gordon J. Brebner, Christopher E. Neely
    Mutable Codesign for Embedded Protocol Processing. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:299-300 [Conf]
  11. Michael Attig, Gordon J. Brebner
    Systematic Characterization of Programmable Packet Processing Pipelines. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:195-204 [Conf]
  12. Jike Chong, Chidamber Kulkarni, Gordon J. Brebner
    Building a flexible and scalable DRAM interface for networking applications on FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:233- [Conf]
  13. Gordon J. Brebner
    A Virtual Hardware Operating System for the Xilinx XC6200. [Citation Graph (0, 0)][DBLP]
    FPL, 1996, pp:327-336 [Conf]
  14. Gordon J. Brebner
    Automatc identification of swappable logic units in XC6200 circuitry. [Citation Graph (0, 0)][DBLP]
    FPL, 1997, pp:173-182 [Conf]
  15. Gordon J. Brebner
    Field-Programmable Logic: Catalyst for New Computing Paradigms. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:49-58 [Conf]
  16. Gordon J. Brebner
    An Interactive Datasheet for the Xilinx XC6200. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:401-405 [Conf]
  17. Gordon J. Brebner, Neil W. Bergmann
    Reconfigurable Computing in Remote and Harsh Environments. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:195-204 [Conf]
  18. Gordon J. Brebner, Oliver Diessel
    Chip-Based Reconfigurable Task Management. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:182-191 [Conf]
  19. Gordon J. Brebner, John Gray
    Use of Reconfigurability in Variable-Length Code Detection at Video Rates. [Citation Graph (0, 0)][DBLP]
    FPL, 1995, pp:429-438 [Conf]
  20. Gordon J. Brebner
    Multithreading for Logic-Centric Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:5-14 [Conf]
  21. Gordon J. Brebner
    Programmable Logic Has More Computational Power than Fixed Logic. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:404-413 [Conf]
  22. Philip James-Roxby, Gordon J. Brebner
    Multithreading in a Hyper-programmable Platform for Networked Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1017-1021 [Conf]
  23. Eric Keller, Gordon J. Brebner, Philip James-Roxby
    Software Decelerators. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:385-395 [Conf]
  24. Todd S. Sproull, Gordon J. Brebner, Christopher E. Neely
    Mutable Codesign for Embedded Protocol Processing. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:51-56 [Conf]
  25. Gordon J. Brebner
    Workshop Introduction. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  26. Gordon J. Brebner, Adam Donlin
    Runtime Reconfigurable Routing. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1998, pp:25-30 [Conf]
  27. Leslie G. Valiant, Gordon J. Brebner
    Universal Schemes for Parallel Communication [Citation Graph (0, 0)][DBLP]
    STOC, 1981, pp:263-277 [Conf]
  28. Tim Kempster, Gordon J. Brebner, Peter Thanisch
    A Transactional Approach to Configuring Telecommunications Services. [Citation Graph (0, 0)][DBLP]
    Databases in Telecommunications, 1999, pp:40-53 [Conf]
  29. Gordon J. Brebner
    A CCS-based Investigation of Deadlock in a Multi-process Electronic Mail System. [Citation Graph (0, 0)][DBLP]
    Formal Asp. Comput., 1993, v:5, n:5, pp:467-478 [Journal]
  30. Chidamber Kulkarni, Gordon J. Brebner
    Micro-Coded Datapaths: Populating the Space Between Finite State Machine and Processor. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  31. Gordon J. Brebner, Samarjit Chakraborty, Weng-Fai Wong
    Editorial for the Special Issue on Field Programmable Technology. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2007, v:47, n:1, pp:1-2 [Journal]

  32. 06141 Abstracts Collection -- Dynamically Reconfigurable Architectures. [Citation Graph (, )][DBLP]


  33. 06141 Executive Summary -- Dynamically Reconfigurable Architectures. [Citation Graph (, )][DBLP]


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