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Bipul Chandra Paul: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy
    Dynamic Noise Analysis with Capacitive and Inductive Coupling. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:65-70 [Conf]
  2. Woopyo Jeong, Bipul Chandra Paul, Kaushik Roy
    Adaptive supply voltage technique for low swing interconnects. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:284-287 [Conf]
  3. Bipul Chandra Paul, Seung Hoon Choi, Yonghee Im, Kaushik Roy
    Design Verification and Robust Design Technique for Cross-Talk Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:449-0 [Conf]
  4. Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy
    Novel sizing algorithm for yield improvement under process variation in nanometer technology. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:454-459 [Conf]
  5. Kunhyuk Kang, Bipul Chandra Paul, Kaushik Roy
    Statistical Timing Analysis using Levelized Covariance Propagation. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:764-769 [Conf]
  6. Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Mohammad Ashraful Alam, Kaushik Roy
    Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:780-785 [Conf]
  7. Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy
    Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:856-861 [Conf]
  8. Amit Agarwal, Bipul Chandra Paul, Kaushik Roy
    A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:149-154 [Conf]
  9. Bipul Chandra Paul, Arijit Raychowdhury, Kaushik Roy
    Device optimization for ultra-low power digital sub-threshold operation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:96-101 [Conf]
  10. Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul
    Robust ultra-low power sub-threshold DTMOS logic. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:25-30 [Conf]
  11. Bipul Chandra Paul, Cassondra Neau, Kaushik Roy
    Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1269-1275 [Conf]
  12. Bipul Chandra Paul, Kaushik Roy
    Testing CrossTalk Induced Delay Faults in Static CMOS Circuits Through Dynamic Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:384-390 [Conf]
  13. Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy
    Dynamic Noise Analysis with Capacitive and Inductive Coupling. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:65-70 [Conf]
  14. Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul
    Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:211-214 [Conf]
  15. Naran Sirisantana, Bipul Chandra Paul, Kaushik Roy
    Enhancing Yield at the End of the Technology Roadmap. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:6, pp:563-571 [Journal]
  16. Bipul Chandra Paul, Amit Agarwal, Kaushik Roy
    Low-power design techniques for scaled technologies. [Citation Graph (0, 0)][DBLP]
    Integration, 2006, v:39, n:2, pp:64-89 [Journal]
  17. Amit Agarwal, Bipul Chandra Paul, Hamid Mahmoodi-Meimand, Animesh Datta, Kaushik Roy
    A process-tolerant cache architecture for improved yield in nanoscale technologies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:27-38 [Journal]
  18. Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy
    Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1213-1224 [Journal]
  19. Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul
    Robust subthreshold logic for ultra-low power operation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:90-99 [Journal]

  20. ROM based logic (RBL) design: High-performance and low-power adders. [Citation Graph (, )][DBLP]


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