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Georgi Gaydadjiev: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Stamatis Vassiliadis, Leonel Sousa, Georgi Gaydadjiev
    The Midlifekicker Microarchitecture Evaluation Metric. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:92-100 [Conf]
  2. A. J. van de Goor, G. N. Gaydadjiev
    Realistic Linked Memory Cell Array Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:183-188 [Conf]
  3. Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev
    Manifestation of Precharge Faults in High Speed DRAM Devices. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:179-184 [Conf]
  4. Georgi Gaydadjiev, Stamatis Vassiliadis
    SCISM vs IA-64 Tagging: Differences/Code Density Effects. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2004, pp:571-577 [Conf]
  5. Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassiliadis
    Visual Data Rectangular Memory. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2004, pp:760-767 [Conf]
  6. Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassiliadis
    The MOLEN Processor Prototype. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:296-299 [Conf]
  7. Yong Dou, Stamatis Vassiliadis, Georgi Kuzmanov, G. N. Gaydadjiev
    64-bit floating-point FPGA matrix multiplication. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:86-95 [Conf]
  8. Melanie R. Rieback, Georgi Gaydadjiev, Bruno Crispo, Rutger F. H. Hofman, Andrew S. Tanenbaum
    A Platform for RFID Security and Privacy Administration (Awarded Best Paper!). [Citation Graph (0, 0)][DBLP]
    LISA, 2006, pp:89-102 [Conf]
  9. Said Hamdioui, Georgi Gaydadjiev, A. J. van de Goor
    The State-of-Art and Future Trends in Testing Embedded Memories. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:54-59 [Conf]
  10. Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassiliadis
    Loading rho-µ-Code: Design Considerations. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:11-19 [Conf]
  11. Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassiliadis
    The Virtex II ProTM MOLEN Processor. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:192-202 [Conf]
  12. Georgi Gaydadjiev, Stamatis Vassiliadis
    Flux Caches: What Are They and Are They Useful? [Citation Graph (0, 0)][DBLP]
    SAMOS, 2005, pp:93-102 [Conf]
  13. Georgi Gaydadjiev, Stamatis Vassiliadis
    SAD Prefetching for MPEG4 Using Flux Caches. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2006, pp:248-258 [Conf]
  14. Stamatis Vassiliadis, Georgi Gaydadjiev, Koen Bertels, Elena Moscu Panainte
    The Molen Programming Paradigm. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:1-10 [Conf]
  15. A. J. van de Goor, G. N. Gaydadjiev, V. G. Mikitjuk, Vyacheslav N. Yarmolik
    March LR: a test for realistic linked faults. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:272-280 [Conf]
  16. Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev
    Optimizing Test Length for Soft Faults in DRAM Devices. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:59-66 [Conf]
  17. Stamatis Vassiliadis, Stephan Wong, Georgi Gaydadjiev, Koen Bertels, Georgi Kuzmanov, Elena Moscu Panainte
    The MOLEN Polymorphic Processor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:11, pp:1363-1375 [Journal]
  18. Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassiliadis
    Multimedia rectangularly addressable memory. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Multimedia, 2006, v:8, n:2, pp:315-322 [Journal]
  19. Humberto Calderon, Carlo Galuzzi, Georgi Gaydadjiev, Stamatis Vassiliadis
    High-Bandwidth Address Generation Unit. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:251-262 [Conf]
  20. Frank Bouwens, Mladen Berekovic, Andreas Kanstein, Georgi Gaydadjiev
    Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:1-13 [Conf]
  21. Stamatis Vassiliadis, Georgi Kuzmanov, Stephan Wong, Elena Moscu Panainte, Georgi Gaydadjiev, Koen Bertels, Dmitry Cheresiz
    PISC: Polymorphic Instruction Set Computers. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:274-286 [Conf]
  22. Dennis Vermoen, Marc F. Witteman, Georgi Gaydadjiev
    Reverse Engineering Java Card Applets Using Power Analysis. [Citation Graph (0, 0)][DBLP]
    WISTP, 2007, pp:138-149 [Conf]

  23. Real-time FPGA-implementation for blue-sky Detection. [Citation Graph (, )][DBLP]


  24. Reconfigurable Universal Adder. [Citation Graph (, )][DBLP]


  25. Evaluating Various Branch-Prediction Schemes for Biomedical-Implant Processors. [Citation Graph (, )][DBLP]


  26. Low power microarchitecture with instruction reuse. [Citation Graph (, )][DBLP]


  27. Profiling of symmetric-encryption algorithms for a novel biomedical-implant architecture. [Citation Graph (, )][DBLP]


  28. Profiling of lossless-compression algorithms for a novel biomedical-implant architecture. [Citation Graph (, )][DBLP]


  29. Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications. [Citation Graph (, )][DBLP]


  30. Memory Organization with Multi-Pattern Parallel Accesses. [Citation Graph (, )][DBLP]


  31. An efficient algorithm for free resources management on the FPGA. [Citation Graph (, )][DBLP]


  32. Intelligent Merging Online Task Placement Algorithm for Partial Reconfigurable Systems. [Citation Graph (, )][DBLP]


  33. March LA: a test for linked memory faults. [Citation Graph (, )][DBLP]


  34. Memory testing with a RISC microcontroller. [Citation Graph (, )][DBLP]


  35. Data path Configuration Time Reduction for Run-time Reconfigurable Systems. [Citation Graph (, )][DBLP]


  36. FPGA accelerator for real-time skin segmentation. [Citation Graph (, )][DBLP]


  37. A 3d-audio reconfigurable processor. [Citation Graph (, )][DBLP]


  38. HARTES Toolchain Early Evaluation: Profiling, Compilation and HDL Generation. [Citation Graph (, )][DBLP]


  39. DWARV: DelftWorkBench Automated Reconfigurable VHDL Generator. [Citation Graph (, )][DBLP]


  40. A Quantitative Prediction Model for Hardware/Software Partitioning. [Citation Graph (, )][DBLP]


  41. Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array. [Citation Graph (, )][DBLP]


  42. Infrastructure for Cross-Layer Designs Interaction. [Citation Graph (, )][DBLP]


  43. SAMS multi-layout memory: providing multiple views of data to boost SIMD performance. [Citation Graph (, )][DBLP]


  44. A self-adaptive on-line task placement algorithm for partially reconfigurable systems. [Citation Graph (, )][DBLP]


  45. Reconfigurable accelerator for WFS-based 3D-audio. [Citation Graph (, )][DBLP]


  46. Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications. [Citation Graph (, )][DBLP]


  47. ImpBench: A novel benchmark suite for biomedical, microelectronic implants. [Citation Graph (, )][DBLP]


  48. OpenMP extensions for FPGA accelerators. [Citation Graph (, )][DBLP]


  49. Vectorized AES Core for High-throughput Secure Environments. [Citation Graph (, )][DBLP]


  50. Cross-Layer Designs Architecture for LEO Satellite Ad Hoc Network. [Citation Graph (, )][DBLP]


  51. Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices. [Citation Graph (, )][DBLP]


  52. Run-time Adaptable Architectures for Heterogeneous Behavior Embedded Systems. [Citation Graph (, )][DBLP]


  53. Online Task Scheduling for the FPGA-Based Partially Reconfigurable Systems. [Citation Graph (, )][DBLP]


  54. A Modified Merging Approach for Datapath Configuration Time Reduction. [Citation Graph (, )][DBLP]


  55. 3D Compaction: A Novel Blocking-Aware Algorithm for Online Hardware Task Scheduling and Placement on 2D Partially Reconfigurable Devices. [Citation Graph (, )][DBLP]


  56. Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture. [Citation Graph (, )][DBLP]


  57. Scalability Analysis of Progressive Alignment on a Multicore. [Citation Graph (, )][DBLP]


  58. A reconfigurable beamformer for audio applications. [Citation Graph (, )][DBLP]


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