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Georgi Gaydadjiev :
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Stamatis Vassiliadis , Leonel Sousa , Georgi Gaydadjiev The Midlifekicker Microarchitecture Evaluation Metric. [Citation Graph (0, 0)][DBLP ] ASAP, 2005, pp:92-100 [Conf ] A. J. van de Goor , G. N. Gaydadjiev Realistic Linked Memory Cell Array Faults. [Citation Graph (0, 0)][DBLP ] Asian Test Symposium, 1996, pp:183-188 [Conf ] Zaid Al-Ars , Said Hamdioui , Georgi Gaydadjiev Manifestation of Precharge Faults in High Speed DRAM Devices. [Citation Graph (0, 0)][DBLP ] DDECS, 2007, pp:179-184 [Conf ] Georgi Gaydadjiev , Stamatis Vassiliadis SCISM vs IA-64 Tagging: Differences/Code Density Effects. [Citation Graph (0, 0)][DBLP ] Euro-Par, 2004, pp:571-577 [Conf ] Georgi Kuzmanov , Georgi Gaydadjiev , Stamatis Vassiliadis Visual Data Rectangular Memory. [Citation Graph (0, 0)][DBLP ] Euro-Par, 2004, pp:760-767 [Conf ] Georgi Kuzmanov , Georgi Gaydadjiev , Stamatis Vassiliadis The MOLEN Processor Prototype. [Citation Graph (0, 0)][DBLP ] FCCM, 2004, pp:296-299 [Conf ] Yong Dou , Stamatis Vassiliadis , Georgi Kuzmanov , G. N. Gaydadjiev 64-bit floating-point FPGA matrix multiplication. [Citation Graph (0, 0)][DBLP ] FPGA, 2005, pp:86-95 [Conf ] Melanie R. Rieback , Georgi Gaydadjiev , Bruno Crispo , Rutger F. H. Hofman , Andrew S. Tanenbaum A Platform for RFID Security and Privacy Administration (Awarded Best Paper!). [Citation Graph (0, 0)][DBLP ] LISA, 2006, pp:89-102 [Conf ] Said Hamdioui , Georgi Gaydadjiev , A. J. van de Goor The State-of-Art and Future Trends in Testing Embedded Memories. [Citation Graph (0, 0)][DBLP ] MTDT, 2004, pp:54-59 [Conf ] Georgi Kuzmanov , Georgi Gaydadjiev , Stamatis Vassiliadis Loading rho-µ-Code: Design Considerations. [Citation Graph (0, 0)][DBLP ] SAMOS, 2004, pp:11-19 [Conf ] Georgi Kuzmanov , Georgi Gaydadjiev , Stamatis Vassiliadis The Virtex II ProTM MOLEN Processor. [Citation Graph (0, 0)][DBLP ] SAMOS, 2004, pp:192-202 [Conf ] Georgi Gaydadjiev , Stamatis Vassiliadis Flux Caches: What Are They and Are They Useful? [Citation Graph (0, 0)][DBLP ] SAMOS, 2005, pp:93-102 [Conf ] Georgi Gaydadjiev , Stamatis Vassiliadis SAD Prefetching for MPEG4 Using Flux Caches. [Citation Graph (0, 0)][DBLP ] SAMOS, 2006, pp:248-258 [Conf ] Stamatis Vassiliadis , Georgi Gaydadjiev , Koen Bertels , Elena Moscu Panainte The Molen Programming Paradigm. [Citation Graph (0, 0)][DBLP ] SAMOS, 2004, pp:1-10 [Conf ] A. J. van de Goor , G. N. Gaydadjiev , V. G. Mikitjuk , Vyacheslav N. Yarmolik March LR: a test for realistic linked faults. [Citation Graph (0, 0)][DBLP ] VTS, 1996, pp:272-280 [Conf ] Zaid Al-Ars , Said Hamdioui , Georgi Gaydadjiev Optimizing Test Length for Soft Faults in DRAM Devices. [Citation Graph (0, 0)][DBLP ] VTS, 2007, pp:59-66 [Conf ] Stamatis Vassiliadis , Stephan Wong , Georgi Gaydadjiev , Koen Bertels , Georgi Kuzmanov , Elena Moscu Panainte The MOLEN Polymorphic Processor. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 2004, v:53, n:11, pp:1363-1375 [Journal ] Georgi Kuzmanov , Georgi Gaydadjiev , Stamatis Vassiliadis Multimedia rectangularly addressable memory. [Citation Graph (0, 0)][DBLP ] IEEE Transactions on Multimedia, 2006, v:8, n:2, pp:315-322 [Journal ] Humberto Calderon , Carlo Galuzzi , Georgi Gaydadjiev , Stamatis Vassiliadis High-Bandwidth Address Generation Unit. [Citation Graph (0, 0)][DBLP ] SAMOS, 2007, pp:251-262 [Conf ] Frank Bouwens , Mladen Berekovic , Andreas Kanstein , Georgi Gaydadjiev Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array. [Citation Graph (0, 0)][DBLP ] ARC, 2007, pp:1-13 [Conf ] Stamatis Vassiliadis , Georgi Kuzmanov , Stephan Wong , Elena Moscu Panainte , Georgi Gaydadjiev , Koen Bertels , Dmitry Cheresiz PISC: Polymorphic Instruction Set Computers. [Citation Graph (0, 0)][DBLP ] ARC, 2006, pp:274-286 [Conf ] Dennis Vermoen , Marc F. Witteman , Georgi Gaydadjiev Reverse Engineering Java Card Applets Using Power Analysis. [Citation Graph (0, 0)][DBLP ] WISTP, 2007, pp:138-149 [Conf ] Real-time FPGA-implementation for blue-sky Detection. [Citation Graph (, )][DBLP ] Reconfigurable Universal Adder. [Citation Graph (, )][DBLP ] Evaluating Various Branch-Prediction Schemes for Biomedical-Implant Processors. [Citation Graph (, )][DBLP ] Low power microarchitecture with instruction reuse. [Citation Graph (, )][DBLP ] Profiling of symmetric-encryption algorithms for a novel biomedical-implant architecture. [Citation Graph (, )][DBLP ] Profiling of lossless-compression algorithms for a novel biomedical-implant architecture. [Citation Graph (, )][DBLP ] Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications. [Citation Graph (, )][DBLP ] Memory Organization with Multi-Pattern Parallel Accesses. [Citation Graph (, )][DBLP ] An efficient algorithm for free resources management on the FPGA. [Citation Graph (, )][DBLP ] Intelligent Merging Online Task Placement Algorithm for Partial Reconfigurable Systems. [Citation Graph (, )][DBLP ] March LA: a test for linked memory faults. [Citation Graph (, )][DBLP ] Memory testing with a RISC microcontroller. [Citation Graph (, )][DBLP ] Data path Configuration Time Reduction for Run-time Reconfigurable Systems. [Citation Graph (, )][DBLP ] FPGA accelerator for real-time skin segmentation. [Citation Graph (, )][DBLP ] A 3d-audio reconfigurable processor. [Citation Graph (, )][DBLP ] HARTES Toolchain Early Evaluation: Profiling, Compilation and HDL Generation. [Citation Graph (, )][DBLP ] DWARV: DelftWorkBench Automated Reconfigurable VHDL Generator. [Citation Graph (, )][DBLP ] A Quantitative Prediction Model for Hardware/Software Partitioning. [Citation Graph (, )][DBLP ] Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array. [Citation Graph (, )][DBLP ] Infrastructure for Cross-Layer Designs Interaction. [Citation Graph (, )][DBLP ] SAMS multi-layout memory: providing multiple views of data to boost SIMD performance. [Citation Graph (, )][DBLP ] A self-adaptive on-line task placement algorithm for partially reconfigurable systems. [Citation Graph (, )][DBLP ] Reconfigurable accelerator for WFS-based 3D-audio. [Citation Graph (, )][DBLP ] Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications. [Citation Graph (, )][DBLP ] ImpBench: A novel benchmark suite for biomedical, microelectronic implants. [Citation Graph (, )][DBLP ] OpenMP extensions for FPGA accelerators. [Citation Graph (, )][DBLP ] Vectorized AES Core for High-throughput Secure Environments. [Citation Graph (, )][DBLP ] Cross-Layer Designs Architecture for LEO Satellite Ad Hoc Network. [Citation Graph (, )][DBLP ] Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices. [Citation Graph (, )][DBLP ] Run-time Adaptable Architectures for Heterogeneous Behavior Embedded Systems. [Citation Graph (, )][DBLP ] Online Task Scheduling for the FPGA-Based Partially Reconfigurable Systems. [Citation Graph (, )][DBLP ] A Modified Merging Approach for Datapath Configuration Time Reduction. [Citation Graph (, )][DBLP ] 3D Compaction: A Novel Blocking-Aware Algorithm for Online Hardware Task Scheduling and Placement on 2D Partially Reconfigurable Devices. [Citation Graph (, )][DBLP ] Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture. [Citation Graph (, )][DBLP ] Scalability Analysis of Progressive Alignment on a Multicore. [Citation Graph (, )][DBLP ] A reconfigurable beamformer for audio applications. [Citation Graph (, )][DBLP ] Search in 0.021secs, Finished in 0.023secs