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Soo-Ik Chae: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ren Huang, Soo-Ik Chae
    Implementation of an OpenVG Rasterizer with Configurable Anti-Aliasing and Multi-Window Scissoring. [Citation Graph (0, 0)][DBLP]
    CIT, 2006, pp:179- [Conf]
  2. Sang-Il Han, Soo-Ik Chae, Ahmed Amine Jerraya
    Functional modeling techniques for efficient SW code generation of video codec applications. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:935-940 [Conf]
  3. Minho Kim, Ingu Hwang, Soo-Ik Chae
    A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:631-634 [Conf]
  4. Seokkee Kim, Jun-Ho Kwon, Soo-Ik Chae
    An 8-b nRERL microprocessor for ultra-low-energy applications. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:27-28 [Conf]
  5. Joonho Lim, Dong-G. Kim, Sang-C. Kang, Soo-Ik Chae
    An 8×8 nRERL serial multiplier for ultra-low-power aplications. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:35-36 [Conf]
  6. Sanggyu Park, Sang-yong Yoon, Soo-Ik Chae
    Reusable component IP design using refinement-based design environment. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:588-593 [Conf]
  7. Seokkee Kim, Soo-Ik Chae
    Implementation of a simple 8-bit microprocessor with reversible energy recovery logic. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2005, pp:421-426 [Conf]
  8. Sang-Il Han, Amer Baghdadi, Marius Bonaciu, Soo-Ik Chae, Ahmed Amine Jerraya
    An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:250-255 [Conf]
  9. Sang-Il Han, Xavier Guerin, Soo-Ik Chae, Ahmed Amine Jerraya
    Buffer memory optimization for video codec application modeled in Simulink. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:689-694 [Conf]
  10. Eel-Wan Lee, Jae-Hee Won, Soo-Ik Chae
    Modified Probabilistic RAM Archticture for VLSI Implementation of a Backpropagation Learning Algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1897-1900 [Conf]
  11. Joonho Lim, Eel-Wan Lee, Soo-Ik Chae
    Character Recognition by Neural Networks with Single-Layer Training and Rejection Mechanism. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:327-330 [Conf]
  12. Seung-Jai Min, Eel-Wan Lee, Soo-Ik Chae
    A Study on the Stochastic Computation Using the Ratio of One Pulses and Zero Pulses. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:471-474 [Conf]
  13. Sungjun Park, Seung-Jai Min, Soo-Ik Chae
    Stereo Correspondence with Discrete-Time Cellular Neural Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:225-228 [Conf]
  14. Seokkee Kim, Soo-Ik Chae
    Complexity reduction in an nRERL microprocessor. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:180-185 [Conf]
  15. Jun-Ho Kwon, Joonho Lim, Soo-Ik Chae
    A three-port nRERL register file for ultra-low-energy applications. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:161-166 [Conf]
  16. Koichi Nose, Soo-Ik Chae, Takayasu Sakurai
    Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session). [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:228-230 [Conf]
  17. Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi
    Partial bus-invert coding for power optimization of system level bus. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:127-129 [Conf]
  18. Sanggyu Park, Soo-Ik Chae
    A Two-Week Program for a Platform-Based SoC Design. [Citation Graph (0, 0)][DBLP]
    MSE, 2005, pp:43-44 [Conf]
  19. Eunseok Song, Young-Kil Park, Soon Kwon, Soo-Ik Chae
    A Cycle-Accurate Energy Estimator for CMOS Digital Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:159-168 [Conf]
  20. Kyung-soo Oh, Sang-yong Yoon, Soo-Ik Chae
    Emulator Environment Based on an FPGA Prototyping Board. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:72-77 [Conf]
  21. Sanggyu Park, Soo-Ik Chae
    A C/C++-Based Functional Verification Framework Using the SystemC Verification Library. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:237-239 [Conf]
  22. Sanggyu Park, Sang-yong Yoon, Soo-Ik Chae
    A Mixed-Level Virtual Prototyping Environment for Refinement-Based Design Environment. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2006, pp:63-68 [Conf]
  23. Eel-Wan Lee, Soo-Ik Chae
    Fast Design of Reduced-Complexity Nearest-Neighbor Classifiers Using Triangular Inequality. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Pattern Anal. Mach. Intell., 1998, v:20, n:5, pp:562-566 [Journal]
  24. Kai Huang, Sang-Il Han, Katalin Popovici, Lisane B. de Brisolara, Xavier Guerin, Lei Li, Xiaolang Yan, Soo-Ik Chae, Luigi Carro, Ahmed Amine Jerraya
    Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:39-42 [Conf]
  25. Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi
    Partial bus-invert coding for power optimization of application-specific systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:377-383 [Journal]

  26. Reducing fine-grain communication overhead in multithread code generation for heterogeneous MPSoC. [Citation Graph (, )][DBLP]

  27. Configurable high-performance video platform using multiple RISC clusters connected with separated data and control networks. [Citation Graph (, )][DBLP]

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