Conferences in DBLP
Walter Davis The CAD challenges of designing low power, high performance VLSI system. [Citation Graph (0, 0)][DBLP ] Conf ] Kimiyoshi Usami , Mark Horowitz Clustered voltage scaling technique for low-power design. [Citation Graph (0, 0)][DBLP ] Conf ] Salil Raje , Majid Sarrafzadeh Variable voltage scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Chetana Nagendra , Robert Michael Owens , Mary Jane Irwin Unifying carry-sum and signed-digital number representations for low power. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Benini , Giovanni De Micheli Transformation and synthesis of FSMs for low-power gated-clock implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Christos A. Papachristou , Mark Spining , Mehrdad Nourani A multiple clocking scheme for low power RTL design. [Citation Graph (0, 0)][DBLP ] Conf ] José Monteiro , Srinivas Devadas Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs. [Citation Graph (0, 0)][DBLP ] Conf ] Peter A. Beerel , Cheng-Ta Hsieh , Suhrid A. Wadekar Estimation of energy consumption in speed-independent control circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Uming Ko , Poras T. Balsara , Ashwini K. Nanda Energy optimization of multi-level processor cache architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Sven Wuytack , Francky Catthoor , Hugo De Man Transforming set data types to power optimal data structures. [Citation Graph (0, 0)][DBLP ] Conf ] Ramesh Panwar , David A. Rennels Reducing the frequency of tag compares for low power I-cache design. [Citation Graph (0, 0)][DBLP ] Conf ] Ching-Long Su , Alvin M. Despain Cache design trade-offs for power and performance optimization: a case study. [Citation Graph (0, 0)][DBLP ] Conf ] Aurobindo Dasgupta , Ramesh Karri Simultaneous scheduling and binding for power minimization during microarchitecture synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Anthony Correale Jr. Overview of the power minimization techniques employed in the IBM PowerPC 4xx embedded controllers. [Citation Graph (0, 0)][DBLP ] Conf ] Diana Marculescu , Radu Marculescu , Massoud Pedram Information theoretic measures of energy consumption at register transfer level. [Citation Graph (0, 0)][DBLP ] Conf ] Farid N. Najm Towards a high-level power estimation capability. [Citation Graph (0, 0)][DBLP ] Conf ] Paul E. Landman , Jan M. Rabaey Activity-sensitive architectural power analysis for the control path. [Citation Graph (0, 0)][DBLP ] Conf ] Enric Musoll , Jordi Cortadella High-level synthesis techniques for reducing the activity of functional units. [Citation Graph (0, 0)][DBLP ] Conf ] Charlie X. Huang , Bill Zhang , An-Chang Deng , Burkhard Swirski The design and implementation of PowerMill. [Citation Graph (0, 0)][DBLP ] Conf ] Abelardo Pardo , R. Iris Bahar , Srilatha Manne , Peter Feldmann , Gary D. Hachtel , Fabio Somenzi CMOS dynamic power estimation based on collapsible current source transistor modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Piguet , Jean-Marc Masgonty , V. von Kaenel , T. Schneider Logic design for low-voltage/low-power CMOS circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Michele Favalli , Luca Benini Analysis of glitch power dissipation in CMOS ICs. [Citation Graph (0, 0)][DBLP ] Conf ] S. Turgis , Nadine Azémard , Daniel Auvergne Explicit evaluation of short circuit power dissipation for CMOS logic structures. [Citation Graph (0, 0)][DBLP ] Conf ] Premal Buch , Shen Lin , Vijay Nagasamy , Ernest S. Kuh Techniques for fast circuit simulation applied to power estimation of CMOS circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Manjit Borah , Robert Michael Owens , Mary Jane Irwin High-throughput and low-power DSP using clocked-CMOS circuitry. [Citation Graph (0, 0)][DBLP ] Conf ] William A. Chren Jr. Low delay-power product CMOS design using one-hot residue coding. [Citation Graph (0, 0)][DBLP ] Conf ] Rafael Fried , Reuven Holzer Low power and EMI, high frequency, crystal oscillator. [Citation Graph (0, 0)][DBLP ] Conf ] M. Tachibana , S. Kurosawa , R. Nojima , Norman Kojima , Masaaki Yamada , Takashi Mitsuhashi , Nobuyuki Goto Power and area optimization by reorganizing CMOS complex gate circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Alexey Glebov , David Blaauw , Larry G. Jones Transistor reordering for low power CMOS gates using an SP-BDD representation. [Citation Graph (0, 0)][DBLP ] Conf ] Manjit Borah , Robert Michael Owens , Mary Jane Irwin Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint. [Citation Graph (0, 0)][DBLP ] Conf ] Vamshi Veeramachaneni , Akhilesh Tyagi , Suresh Rajgopal Re-encoding for low power state assignment of FSMs. [Citation Graph (0, 0)][DBLP ] Conf ] Jae W. Chung , De-Yu Kao , Chung-Kuan Cheng , Ting-Ting Y. Lin Optimization of power dissipation and skew sensitivity in clock buffer synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Kei-Yong Khoo , Alan N. Willson Jr. Charge recovery on a databus. [Citation Graph (0, 0)][DBLP ] Conf ] Alan Kramer , John S. Denker , B. Flower , J. Moroney 2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits. [Citation Graph (0, 0)][DBLP ] Conf ] David J. Frank , Paul M. Solomon Electroid-oriented adiabatic switching circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Alan Kramer , Roberto Canegallo , Mauro Chinosi , D. Doise , Giovanni Gozzini , Pier Luigi Rolandi , M. Sabatini , P. Zabberoni Ultra-low-power analog associative memory core using flash-EEPROM-based programmable capacitors. [Citation Graph (0, 0)][DBLP ] Conf ] Phillip E. Allen , Benjamin J. Blalock , Gabriel A. Rincon Low voltage analog circuits using standard CMOS technology. [Citation Graph (0, 0)][DBLP ] Conf ] Anthony M. Hill , Sung-Mo Kang Determining accuracy bounds for simulation-based switching activity estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Vivek Tiwari , Sharad Malik , Pranav Ashar Guarded evaluation: pushing power management to logic synthesis/design. [Citation Graph (0, 0)][DBLP ] Conf ] Christopher K. Lennard , A. Richard Newton An estimation technique to guide low power resynthesis algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] 