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Santosh G. Abraham :
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Santosh G. Abraham , Waleed Meleis , Ivan D. Baev Efficient Backtracking Instruction Schedulers. [Citation Graph (0, 0)][DBLP ] IEEE PACT, 2000, pp:301-308 [Conf ] Robert Schreiber , Shail Aditya , B. Ramakrishna Rau , Vinod Kathail , Scott A. Mahlke , Santosh G. Abraham , Greg Snider High-Level Synthesis of Nonprogrammable Hardware Accelerators. [Citation Graph (0, 0)][DBLP ] ASAP, 2000, pp:113-0 [Conf ] William H. Mangione-Smith , Santosh G. Abraham , Edward S. Davidson Vector Register Design for Polycyclic Vector Scheduling. [Citation Graph (0, 0)][DBLP ] ASPLOS, 1991, pp:154-163 [Conf ] Santosh G. Abraham , B. Ramakrishna Rau Efficient design space exploration in PICO. [Citation Graph (0, 0)][DBLP ] CASES, 2000, pp:71-79 [Conf ] Santosh G. Abraham , Rabin A. Sugumar Fast Efficient Simulation of Write-Buffer Configurations. [Citation Graph (0, 0)][DBLP ] HICSS (1), 1994, pp:231-240 [Conf ] Alexandre E. Eichenberger , Santosh G. Abraham Modeling load imbalance and fuzzy barriers for scalable shared-memory multiprocessors. [Citation Graph (0, 0)][DBLP ] HICSS (1), 1995, pp:262-271 [Conf ] Lawrence Spracklen , Santosh G. Abraham Chip Multithreading: Opportunities and Challenges. [Citation Graph (0, 0)][DBLP ] HPCA, 2005, pp:248-252 [Conf ] Lawrence Spracklen , Yuan Chou , Santosh G. Abraham Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications. [Citation Graph (0, 0)][DBLP ] HPCA, 2005, pp:225-236 [Conf ] Gautam B. Singh , Santosh G. Abraham , Franklin H. Westervelt Computing Radiosity Solution on a High Performance Workstation LAN. [Citation Graph (0, 0)][DBLP ] HPDC, 1992, pp:248-257 [Conf ] Santosh G. Abraham , Edward S. Davidson A Communication Model for Optimizing Hierarchical Multiprocessor Systems. [Citation Graph (0, 0)][DBLP ] ICPP, 1986, pp:467-474 [Conf ] Santosh G. Abraham , Timothy A. Davis Blocking for Parallel Sparse Linear System Solvers. [Citation Graph (0, 0)][DBLP ] ICPP (1), 1988, pp:166-173 [Conf ] Santosh G. Abraham , Janak H. Patel Parallel Garbage Collection on a Virtual Memory System. [Citation Graph (0, 0)][DBLP ] ICPP, 1987, pp:243-246 [Conf ] Alexandre E. Eichenberger , Santosh G. Abraham Impact of Load Imbalance on the Design of Software Barriers. [Citation Graph (0, 0)][DBLP ] ICPP (2), 1995, pp:63-72 [Conf ] Jiajen M. Lin , Santosh G. Abraham Discrete Event Simulation on Shared Memory Multiprocessors Using Global Simulation Information. [Citation Graph (0, 0)][DBLP ] ICPP (3), 1992, pp:254-261 [Conf ] Rabin A. Sugumar , Santosh G. Abraham Parallel Simulation of Fully Associative Caches. [Citation Graph (0, 0)][DBLP ] ICPP (2), 1991, pp:304-305 [Conf ] Karen A. Tomko , Santosh G. Abraham Iteration Partitioning for Resolving Stride Conflicts on Cache-Coherent Multiprocessors. [Citation Graph (0, 0)][DBLP ] ICPP, 1993, pp:95-102 [Conf ] Eric L. Boyd , John-David Wellman , Santosh G. Abraham , Edward S. Davidson Evaluating the Communication Performance of MPPs Using Synthetic Sparse Matrix Multiplication Workloads. [Citation Graph (0, 0)][DBLP ] International Conference on Supercomputing, 1993, pp:240-250 [Conf ] Alexandre E. Eichenberger , Edward S. Davidson , Santosh G. Abraham Optimum Modulo Schedules for Minimum Register Requirements. [Citation Graph (0, 0)][DBLP ] International Conference on Supercomputing, 1995, pp:31-40 [Conf ] David E. Hudak , Santosh G. Abraham Compiler techniques for data partitioning of sequentially iterated parallel loops. [Citation Graph (0, 0)][DBLP ] ICS, 1990, pp:187-200 [Conf ] David E. Hudak , Santosh G. Abraham Beyond loop partitioning: data assignment and overlap to reduce communication overhead. [Citation Graph (0, 0)][DBLP ] ICS, 1991, pp:172-182 [Conf ] Sorin Iacobovici , Lawrence Spracklen , Sudarshan Kadambi , Yuan Chou , Santosh G. Abraham Effective stream-based and execution-based data prefetching. [Citation Graph (0, 0)][DBLP ] ICS, 2004, pp:1-11 [Conf ] William H. Mangione-Smith , Santosh G. Abraham , Edward S. Davidson Register requirements of pipelined processors. [Citation Graph (0, 0)][DBLP ] ICS, 1992, pp:260-271 [Conf ] Karen A. Tomko , Santosh G. Abraham Data and program restructuring of irregular applications for cache-coherent multiprocessor. [Citation Graph (0, 0)][DBLP ] International Conference on Supercomputing, 1994, pp:214-225 [Conf ] Daniel Windheiser , Eric L. Boyd , Eric Hao , Santosh G. Abraham , Edward S. Davidson KSR 1 Multiprocessor: Analysis of Latency Hiding Techniques in a Sparse Solver. [Citation Graph (0, 0)][DBLP ] IPPS, 1993, pp:454-461 [Conf ] Yang Zeng , Santosh G. Abraham Partitioning regular grid applications with irregular boundaries for cache-coherent multiprocessors. [Citation Graph (0, 0)][DBLP ] IPPS, 1995, pp:222-228 [Conf ] Yuan Chou , Brian Fahs , Santosh G. Abraham Microarchitecture Optimizations for Exploiting Memory-Level Parallelism. [Citation Graph (0, 0)][DBLP ] ISCA, 2004, pp:76-89 [Conf ] Harit Modi , Lawrence Spracklen , Yuan Chou , Santosh G. Abraham Accurate Modeling of Aggressive Speculation in Modern Microprocessor Architectures. [Citation Graph (0, 0)][DBLP ] MASCOTS, 2005, pp:75-84 [Conf ] Santosh G. Abraham , Vinod Kathail , Brian L. Deitrich Meld Scheduling: Relaxing Scheduling Constraints Across Region Boundaries. [Citation Graph (0, 0)][DBLP ] MICRO, 1996, pp:308-321 [Conf ] Santosh G. Abraham , Scott A. Mahlke Automatic and Efficient Evaluation of Memory Hierarchies for Embedded Systems. [Citation Graph (0, 0)][DBLP ] MICRO, 1999, pp:114-125 [Conf ] Santosh G. Abraham , Rabin A. Sugumar , Daniel Windheiser , B. Ramakrishna Rau , Rajiv Gupta Predictability of load/store instruction latencies. [Citation Graph (0, 0)][DBLP ] MICRO, 1993, pp:139-152 [Conf ] Yuan Chou , Lawrence Spracklen , Santosh G. Abraham Store Memory-Level Parallelism Optimizations for Commercial Applications. [Citation Graph (0, 0)][DBLP ] MICRO, 2005, pp:183-196 [Conf ] Alexandre E. Eichenberger , Edward S. Davidson , Santosh G. Abraham Minimum register requirements for a modulo schedule. [Citation Graph (0, 0)][DBLP ] MICRO, 1994, pp:75-84 [Conf ] Jiwei Lu , Abhinav Das , Wei-Chung Hsu , Khoa Nguyen , Santosh G. Abraham Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP Processor. [Citation Graph (0, 0)][DBLP ] MICRO, 2005, pp:93-104 [Conf ] Rabin A. Sugumar , Santosh G. Abraham Efficient Simulation of Caches under Optimal Replacement with Applications to Miss Characterization. [Citation Graph (0, 0)][DBLP ] SIGMETRICS, 1993, pp:24-35 [Conf ] William H. Mangione-Smith , Santosh G. Abraham , Edward S. Davidson A Performance Comparison of the IBM RS/6000 and the Astronautics ZS-1. [Citation Graph (0, 0)][DBLP ] IEEE Computer, 1991, v:24, n:1, pp:39-46 [Journal ] Jiajen M. Lin , Santosh G. Abraham Fast High-Level Simulation of Shared-Memory Multiprocessor Systems. [Citation Graph (0, 0)][DBLP ] International Journal in Computer Simulation, 1992, v:2, n:1, pp:- [Journal ] Santosh G. Abraham , Vinod Kathail , Brian L. Deitrich Meld Scheduling: A Technique for Relaxing Scheduling Constraints. [Citation Graph (0, 0)][DBLP ] International Journal of Parallel Programming, 1998, v:26, n:4, pp:349-381 [Journal ] Ivan D. Baev , Waleed Meleis , Santosh G. Abraham Backtracking-Based Instruction Scheduling to Fill Branch Delay Slots. [Citation Graph (0, 0)][DBLP ] International Journal of Parallel Programming, 2002, v:30, n:6, pp:397-418 [Journal ] David E. Hudak , Santosh G. Abraham Compile-Time Optimization of Near-Neighbor Communication for Scalable Shared Memory Architecture. [Citation Graph (0, 0)][DBLP ] J. Parallel Distrib. Comput., 1992, v:15, n:4, pp:351-367 [Journal ] Jiajen M. Lin , Santosh G. Abraham Utilizing Global Simulation Information in Conservative Parallel Simulation on Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] J. Parallel Distrib. Comput., 1993, v:18, n:4, pp:516-523 [Journal ] Rabin A. Sugumar , Santosh G. Abraham Set-Associative Cache Simulation Using Generalized Binomial Trees [Citation Graph (0, 0)][DBLP ] ACM Trans. Comput. Syst., 1995, v:13, n:1, pp:32-56 [Journal ] Santosh G. Abraham , David E. Hudak Compile-Time Partitioning of Iterative Parallel Loops to Reduce Cache Coherency Traffic. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Parallel Distrib. Syst., 1991, v:2, n:3, pp:318-328 [Journal ] Search in 0.006secs, Finished in 0.284secs