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Victor V. Zyuban: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Victor V. Zyuban
    Unified architecture level energy-efficiency metric. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:24-29 [Conf]
  2. Victor V. Zyuban, Sameh W. Asaad, Thomas W. Fox, Anne-Marie Haen, Daniel Littrell, Jaime H. Moreno
    Design methodology for semi custom processor cores. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:448-452 [Conf]
  3. Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Rick Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler
    Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:238-242 [Conf]
  4. Rakesh Kumar, Victor V. Zyuban, Dean M. Tullsen
    Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:408-419 [Conf]
  5. Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor V. Zyuban, Hans M. Jacobson, Pradip Bose
    Microarchitectural techniques for power gating of execution units. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:32-37 [Conf]
  6. Victor V. Zyuban, Peter M. Kogge
    Optimization of high-performance superscalar architectures for energy efficiency. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:84-89 [Conf]
  7. Victor V. Zyuban, Stephen V. Kosonocky
    Low power integrated scan-retention mechanism. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:98-102 [Conf]
  8. Victor V. Zyuban, Peter M. Kogge
    The energy complexity of register files. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:305-310 [Conf]
  9. Victor V. Zyuban, D. Meltzer
    Clocking strategies and scannable latches for low power appliacations. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:346-351 [Conf]
  10. Victor V. Zyuban, Philip N. Strenski
    Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:166-171 [Conf]
  11. Viji Srinivasan, David Brooks, Michael Gschwind, Pradip Bose, Victor V. Zyuban, Philip N. Strenski, Philip G. Emma
    Optimizing pipelines for power and performance. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:333-344 [Conf]
  12. Pradip Bose, David Brooks, Alper Buyuktosunoglu, Peter W. Cook, K. Das, Philip G. Emma, Michael Gschwind, Hans M. Jacobson, Tejas Karkhanis, Prabhakar Kudva, Stanley Schuster, James E. Smith, Viji Srinivasan, Victor V. Zyuban, David H. Albonesi, Sandhya Dwarkadas
    Early-Stage Definition of LPX: A Low Power Issue-Execute Processor. [Citation Graph (0, 0)][DBLP]
    PACS, 2002, pp:1-17 [Conf]
  13. Stephen V. Kosonocky, Azeez J. Bhavnagarwala, Kenneth Chin, George Gristede, Anne-Marie Haen, Wei Hwang, Mark B. Ketchen, Suhwan Kim, Daniel R. Knebel, Kevin Warren, Victor V. Zyuban
    Low-power circuits and technology for wireless digital systems. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2003, v:47, n:2-3, pp:283-298 [Journal]
  14. Jaime H. Moreno, Victor V. Zyuban, Uzi Shvadron, Fredy D. Neeser, Jeff H. Derby, Malcolm S. Ware, Krishnan Kailas, Ayal Zaks, Amir B. Geva, Shay Ben-David, Sameh W. Asaad, Thomas W. Fox, Daniel Littrell, Marina Biberstein, Dorit Naishlos, Hillery C. Hunter
    An innovative low-power high-performance programmable signal processor for digital communications. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2003, v:47, n:2-3, pp:299-326 [Journal]
  15. Victor V. Zyuban, Philip N. Strenski
    Balancing hardware intensity in microprocessor pipelines. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2003, v:47, n:5-6, pp:585-598 [Journal]
  16. David Brooks, Pradip Bose, Stanley Schuster, Hans M. Jacobson, Prabhakar Kudva, Alper Buyuktosunoglu, John-David Wellman, Victor V. Zyuban, Manish Gupta, Peter W. Cook
    Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2000, v:20, n:6, pp:26-44 [Journal]
  17. Victor V. Zyuban, David Brooks, Viji Srinivasan, Michael Gschwind, Pradip Bose, Philip N. Strenski, Philip G. Emma
    Integrated Analysis of Power and Performance for Pipelined Microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:8, pp:1004-1016 [Journal]
  18. Victor V. Zyuban, Peter M. Kogge
    Inherently Lower-Power High-Performance Superscalar Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:3, pp:268-285 [Journal]
  19. Jeonghee Shin, Victor V. Zyuban, Zhigang Hu, Jude A. Rivers, Pradip Bose
    A Framework for Architecture-Level Lifetime Reliability Modeling. [Citation Graph (0, 0)][DBLP]
    DSN, 2007, pp:534-543 [Conf]
  20. Victor V. Zyuban, Peter M. Kogge
    Application of STD to latch-power estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:111-115 [Journal]
  21. Victor V. Zyuban
    Optimization of scannable latches for low energy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:778-788 [Journal]

  22. Power-efficient, reliable microprocessor architectures: modeling and design methods. [Citation Graph (, )][DBLP]


  23. A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime. [Citation Graph (, )][DBLP]


  24. The opportunity cost of low power design: a case study in circuit tuning. [Citation Graph (, )][DBLP]


  25. A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR). [Citation Graph (, )][DBLP]


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