Journals in DBLP

IEEE Trans. on CAD of Integrated Circuits and Systems
2004, volume: 23, number: 12

1. Ulrich Brenner, Jens Vygen
   Legalizing a placement with minimum total movement. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1597-1613 [Journal]
   
2. Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif
   A methodology for the simultaneous design of supply and signal networks. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1614-1624 [Journal]
   
3. Gunnar Braun, Achim Nohl, Andreas Hoffmann, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr
   A universal technique for fast and flexible instruction-set architecture simulation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1625-1639 [Journal]
   
4. Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
   On the characterization and efficient computation of hard-to-detect bridging faults. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1640-1649 [Journal]
   
5. Biplab K. Sikdar, Niloy Ganguly, Parimal Pal Chaudhuri
   Generation of test patterns without prohibited pattern set. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1650-1660 [Journal]
   
6. Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan
   Closed-form delay and slew metrics made easy. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1661-1669 [Journal]
   
7. Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
   Postroute gate sizing for crosstalk noise reduction. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1670-1677 [Journal]
   
8. Tom Chen, Amjad Hajjar
   Statistical timing analysis of coupled interconnects using quadratic delay-change characteristics. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1677-1683 [Journal]
   
9. Jason Cong, Sung Kyu Lim
   Retiming-based timing analysis with an application to mincut-based global placement. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1684-1692 [Journal]
   
10. Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
    An efficient technique for exploring register file size in ASIP design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1693-1699 [Journal]