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Parimal Pal Chaudhuri: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Niloy Ganguly, Pradipta Maji, Sandip Dhar, Biplab K. Sikdar, Parimal Pal Chaudhuri
    Evolving Cellular Automata as Pattern Classifier. [Citation Graph (0, 0)][DBLP]
    ACRI, 2002, pp:56-68 [Conf]
  2. Sukanta Das, Biplab K. Sikdar, Parimal Pal Chaudhuri
    Characterization of Reachable/Nonreachable Cellular Automata States. [Citation Graph (0, 0)][DBLP]
    ACRI, 2004, pp:813-822 [Conf]
  3. Nirmalya Sundar Maiti, Shiladitya Munshi, P. Pal Chaudhuri
    An Analytical Formulation for Cellular Automata (CA) Based Solution of Density Classification Task (DCT). [Citation Graph (0, 0)][DBLP]
    ACRI, 2006, pp:147-156 [Conf]
  4. Pradipta Maji, Niloy Ganguly, Sourav Saha, Anup K. Roy, Parimal Pal Chaudhuri
    Cellular Automata Machine for Pattern Recognition. [Citation Graph (0, 0)][DBLP]
    ACRI, 2002, pp:270-281 [Conf]
  5. Pradipta Maji, Biplab K. Sikdar, Parimal Pal Chaudhuri
    Cellular Automata Evolution for Distributed Data Mining. [Citation Graph (0, 0)][DBLP]
    ACRI, 2004, pp:40-49 [Conf]
  6. Pradipta Maji, Biplab K. Sikdar, Parimal Pal Chaudhuri
    Cellular Automata Evolution for Pattern Classification. [Citation Graph (0, 0)][DBLP]
    ACRI, 2004, pp:660-669 [Conf]
  7. Monalisa Mukherjee, Niloy Ganguly, Parimal Pal Chaudhuri
    Cellular Automata Based Authentication (CAA). [Citation Graph (0, 0)][DBLP]
    ACRI, 2002, pp:259-269 [Conf]
  8. Chandrama Shaw, Pradipta Maji, Sourav Saha, Biplab K. Sikdar, Samir Roy, Parimal Pal Chaudhuri
    Cellular Automata Based Encompression Technology for Voice Data. [Citation Graph (0, 0)][DBLP]
    ACRI, 2004, pp:258-267 [Conf]
  9. Niloy Ganguly, Pradipta Maji, Arijit Das, Biplab K. Sikdar, Parimal Pal Chaudhuri
    Characterization of Non-linear Cellular Automata Model for Pattern Recognition. [Citation Graph (0, 0)][DBLP]
    AFSS, 2002, pp:214-220 [Conf]
  10. Sukanta Das, Debdas Dey, Subhayan Sen, Biplab K. Sikdar, Parimal Pal Chaudhuri
    An efficient design of non-linear CA based PRPG for VLSI circuit testing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:110-112 [Conf]
  11. Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri
    Design of An On-Chip Test Pattern Generator Without Prohibited Pattern Set (PPS). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:689-696 [Conf]
  12. Baidya Nath Ray, Parimal Pal Chaudhuri, Prasanta Kumar Nandi
    Test Solution For OTA Based Analog Circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:773-788 [Conf]
  13. Biplab K. Sikdar, Debesh K. Das, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee, Parimal Pal Chaudhuri
    Cellular automata as a built in self test structure. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:319-324 [Conf]
  14. Marly Roncken, Ken S. Stevens, Rajesh Pendurkar, Shai Rotem, Parimal Pal Chaudhuri
    CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:62-72 [Conf]
  15. Sukanta Das, Biplab K. Sikdar, Parimal Pal Chaudhuri
    Nonlinear CA Based Scalable Design of On-Chip TPG for Multiple Cores. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:331-334 [Conf]
  16. Sukanta Das, Anirban Kundu, Subhayan Sen, Biplab K. Sikdar, Parimal Pal Chaudhuri
    Non-Linear Celluar Automata Based PRPG Design (Without Prohibited Pattern Set) In Linear Time Complexity. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:78-83 [Conf]
  17. Niloy Ganguly, Anindyasundar Nandi, Sukanta Das, Biplab K. Sikdar, Parimal Pal Chaudhuri
    An Evolutionary Strategy To Design An On-Chip Test Pattern Generator Without Prohibited Pattern Set (PPS). [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:260-265 [Conf]
  18. S. Nandi, Parimal Pal Chaudhuri
    Theory and applications of cellular automata for synthesis of easily testable combinational logic. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:146-152 [Conf]
  19. Kolin Paul, A. Roy, Prasanta Kumar Nandi, B. N. Roy, M. Deb Purkayastha, Santanu Chattopadhyay, Parimal Pal Chaudhuri
    Theory and Application of Multiple Attractor Cellular Automata for Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:388-0 [Conf]
  20. Biplab K. Sikdar, Niloy Ganguly, Aniket Karmakar, Subha Sankar Chowdhury, Parimal Pal Chaudhuri
    Multiple Attractor Cellular Automata for Hierarchical Diagnosis of VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:385-390 [Conf]
  21. Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy
    Fsimac: a fault simulator for asynchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:114-119 [Conf]
  22. Pradipta Maji, Parimal Pal Chaudhuri
    FMACA: A Fuzzy Cellular Automata Based Pattern Classifier. [Citation Graph (0, 0)][DBLP]
    DASFAA, 2004, pp:494-505 [Conf]
  23. Niloy Ganguly, Arijit Das, Pradipta Maji, Biplab K. Sikdar, Parimal Pal Chaudhuri
    Evolving Cellular Automata Based Associative Memory for Pattern Recognition. [Citation Graph (0, 0)][DBLP]
    HiPC, 2001, pp:115-124 [Conf]
  24. Kolin Paul, Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri
    Cellular Automata Based Transform Coding for Image Compression. [Citation Graph (0, 0)][DBLP]
    HiPC, 1999, pp:269-273 [Conf]
  25. Biswadip Mitra, Preeti Ranjan Panda, Parimal Pal Chaudhuri
    A Flexible Scheme for State Assignment Based on Characteristics of the FSM. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:226-229 [Conf]
  26. J. S. R. Subrahmanium, Parimal Pal Chaudhuri, Pabitra Pal Chaudhuri
    Design of a 'T' Fault Repairable Multiprocessor System. [Citation Graph (0, 0)][DBLP]
    ICDCS, 1985, pp:227-233 [Conf]
  27. Subhayan Sen, Chandrama Shaw, Dipanwita Roy Chowdhury, Niloy Ganguly, Parimal Pal Chaudhuri
    Cellular Automata Based Cryptosystem (CAC). [Citation Graph (0, 0)][DBLP]
    ICICS, 2002, pp:303-314 [Conf]
  28. Pradipta Maji, Parimal Pal Chaudhuri
    Cellular Automata Based Pattern Classifying Machine for Distributed Data Mining. [Citation Graph (0, 0)][DBLP]
    ICONIP, 2004, pp:848-853 [Conf]
  29. Pradipta Maji, Rishi Nandi, Parimal Pal Chaudhuri
    Application of Fuzzy Cellular Automata (FCA) For Modeling Tree-Structured Pattern Classifier. [Citation Graph (0, 0)][DBLP]
    IICAI, 2003, pp:1220-1233 [Conf]
  30. S. Nandi, Ch. Rambabu, Parimal Pal Chaudhuri
    A VLSI Architecture for Cellular Automata Based Reed-Solomon Decoder. [Citation Graph (0, 0)][DBLP]
    ISPAN, 1999, pp:158-167 [Conf]
  31. S. Bhattacharjee, J. Bhattacharya, U. Raghavendra, Debashis Saha, Parimal Pal Chaudhuri
    A VLSI architecture for cellular automata based parallel data compression. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:270-275 [Conf]
  32. Partha Sarathi Bhattacharjee, Sajal K. Das, Debashis Saha, D. Roychowdhury, Parimal Pal Chaudhuri
    A Parallel Architecture for Video Compression. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:247-252 [Conf]
  33. Santanu Chattopadhyay, Parimal Pal Chaudhuri
    Parallel Decoder for Cellular Automata Based Byte Error Correcting Code. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:527-528 [Conf]
  34. Santanu Chattopadhyay, Parimal Pal Chaudhuri
    Genetic Algorithm Based Approach for Integrated State Assignment and Flipflop Selection in Finite State Machine Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:522-527 [Conf]
  35. Santanu Chattopadhyay, Parimal Pal Chaudhuri
    Efficient Signatures with Linear Space Complexity for Detecting Boolean Function Equivalence. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:564-0 [Conf]
  36. Santanu Chattopadhyay, Dipanwita Roy Chowdhury, Subarna Bhattacharjee, Parimal Pal Chaudhuri
    Board level fault diagnosis using cellular automata array. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:343-348 [Conf]
  37. Santanu Chattopadhyay, S. Mitra, Parimal Pal Chaudhuri
    Cellular automata based architecture of a database query processor. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:320-321 [Conf]
  38. Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri
    Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:57-62 [Conf]
  39. Parimal Pal Chaudhuri, Dipanwita Roy Chowdhury, Kolin Paul, Biplab K. Sikdar
    Theory and Applications of Cellular Automata for VLSI Design and Testing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:4- [Conf]
  40. Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri
    Architecture for VLSI Design of CA Based Byte Error Correcting Code Decoders. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:283-286 [Conf]
  41. Dipanwita Roy Chowdhury, Supratik Chakraborty, Parimal Pal Chaudhuri
    Synthesis of Self-Checking Sequential Machines Using Cellular Automata. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:107- [Conf]
  42. Sukanta Das, Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri
    Design Of A Universal BIST (UBIST) Structure. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:161-166 [Conf]
  43. Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri
    Design of an On-Chip Test Pattern Generator without Prohibited Pattern Set (PPS). [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:689-0 [Conf]
  44. Susanta Misra, Biswadip Mitra, Parimal Pal Chaudhuri
    A Novel Scheme for Synthesis of Easily Testable Finite State Machines Using Cellular Automata. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:335-340 [Conf]
  45. Biswadip Mitra, Parimal Pal Chaudhuri
    A Scheme for Synthesizing Testable VLSI Designs with Minimum Area Overhead. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:112- [Conf]
  46. S. Mitra, S. Das, Parimal Pal Chaudhuri, S. Nandi
    Architecture of a VLSI Chip for Modeling Amino Acid Sequence in Proteins. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:316-317 [Conf]
  47. S. Nandi, Vamsi Boppana, Parimal Pal Chaudhuri
    A CAD Tool for Design of On-Chip Store & Generate Scheme. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:169-174 [Conf]
  48. S. Nandi, Vamsi Boppana, Supratik Chakraborty, Parimal Pal Chaudhuri, Samir Roy
    Delay Fault Test Generation with Cellular Automata. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:281-286 [Conf]
  49. S. Nandi, Santanu Chattopadhyay, Parimal Pal Chaudhuri
    Programmable cellular automata based testbed for fault diagnosis in VLSI circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:61-64 [Conf]
  50. Kolin Paul, Parimal Pal Chaudhuri, Dipanwita Roy Chowdhury
    Scalable Pipelined Micro-Architecture for Wavelet Transform. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:144-0 [Conf]
  51. Kolin Paul, P. Dutta, Dipanwita Roy Chowdhury, Prasanta Kumar Nandi, Parimal Pal Chaudhuri
    A VLSI Architecture for On-Line Image Decompression Using GF(28) Cellular Automata. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:532-537 [Conf]
  52. Baidya Nath Ray, Parimal Pal Chaudhuri, Prasanta Kumar Nandi
    Design of OTA Based Field Programmable Analog Array. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:492-497 [Conf]
  53. Baidya Nath Ray, Parimal Pal Chaudhuri, Prasanta Kumar Nandi
    Test Solution for OTA Based Analog Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:773-0 [Conf]
  54. Baidya Nath Ray, Parimal Pal Chaudhuri, Prasanta Kumar Nandi, P. K. Ghosh
    Synthesis Of Programmable Current Mode Linear Analog Circuit. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:507-512 [Conf]
  55. Subhayan Sen, Sk. Iqbal Hossain, Kabirul Islam, Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri
    Cryptosystem Designed for Embedded System Security. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:271-276 [Conf]
  56. Chandrama Shaw, Debashis Chatterji, Pradipta Maji, Subhayan Sen, B. N. Roy, Parimal Pal Chaudhuri
    A Pipeline Architecture for Encompression (Encryption + Compression) Technology. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:277-282 [Conf]
  57. Biplab K. Sikdar, Purnabha Majumder, Parimal Pal Chaudhuri, Niloy Ganguly
    Design Of Multiple Attractor Gf (2p) Cellular AutomataFor Diagnosis Of Vlsi Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:454-459 [Conf]
  58. Biplab K. Sikdar, Purnabha Majumder, Monalisa Mukherjee, Parimal Pal Chaudhuri, Debesh K. Das, Niloy Ganguly
    Hierarchical Cellular Automata As An On-Chip Test Pattern Generator. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:403-0 [Conf]
  59. Biplab K. Sikdar, Kolin Paul, Gosta Pada Biswas, Parimal Pal Chaudhuri, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee
    Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:556-561 [Conf]
  60. Biswadip Mitra, Preeti Ranjan Panda, Parimal Pal Chaudhuri
    Estimating the Complexity of Synthesized Designs from FSM Specifications. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1993, v:10, n:1, pp:30-35 [Journal]
  61. Pradipta Maji, Chandrama Shaw, Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri
    Theory and Application of Cellular Automata For Pattern Classification. [Citation Graph (0, 0)][DBLP]
    Fundam. Inform., 2003, v:58, n:2003, pp:321-354 [Journal]
  62. Niloy Ganguly, Pradipta Maji, Biplab K. Sikdar, Parimal Pal Chaudhuri
    Generalized Multiple Attractor Cellular Automata (GMACA) Model for Associative Memory. [Citation Graph (0, 0)][DBLP]
    IJPRAI, 2002, v:16, n:7, pp:781-796 [Journal]
  63. Dipanwita Roy Chowdhury, P. Subbarao, Parimal Pal Chaudhuri
    Characterization of two-dimensional cellular automata using matrix algebra. [Citation Graph (0, 0)][DBLP]
    Inf. Sci., 1993, v:71, n:3, pp:289-314 [Journal]
  64. Aloke K. Das, Tapas K. Nayak, Parimal Pal Chaudhuri
    On characterization of state transition graph of additive cellular automata based on depth. [Citation Graph (0, 0)][DBLP]
    Inf. Sci., 1992, v:65, n:3, pp:189-224 [Journal]
  65. Supratik Chakraborty, Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri
    Theory and Application of Nongroup Cellular Automata for Synthesis of Easily Testable Finite State Machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:7, pp:769-781 [Journal]
  66. Santanu Chattopadhyay, Dipanwita Roy Chowdhury, Subarna Bhattacharjee, Parimal Pal Chaudhuri
    Cellular-Automata-Array-Based Diagnosis of Board Level Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:8, pp:817-828 [Journal]
  67. Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri
    Synthesis of Highly Testable Fixed-Polarity AND-XOR Canonical Networks-A Genetic Algorithm-Based Approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:4, pp:487-490 [Journal]
  68. Dipanwita Roy Chowdhury, Idranil Sen Gupta, Parimal Pal Chaudhuri
    A Low-Cost High-Capacity Associative Memory Design Using Cellular Automata. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:10, pp:1260-1264 [Journal]
  69. Dipanwita Roy Chowdhury, Indranil Sengupta, Parimal Pal Chaudhuri
    CA-Based Byte Error-Correcting Code. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:3, pp:371-382 [Journal]
  70. Dipanwita Roy Chowdhury, Saugata Basu, Idranil Sen Gupta, Parimal Pal Chaudhuri
    Design of CAECC-Cellular Automata Based Error Correcting Code. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:6, pp:759-764 [Journal]
  71. Aloke K. Das, Parimal Pal Chaudhuri
    Vector Space Theoretic Analysis of Additive Cellular Automata and Its Application for Pseudoexhaustive Test Pattern Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:3, pp:340-352 [Journal]
  72. Prabir Dasgupta, Santanu Chattopadhyay, Parimal Pal Chaudhuri, Indranil Sengupta
    Cellular Automata-Based Recursive Pseudoexhaustive Test Pattern Generator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:2, pp:177-185 [Journal]
  73. S. Nandi, Parimal Pal Chaudhuri
    Analysis of Periodic and Intermediate Boundary 90/150 Cellular Automata. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:1, pp:1-12 [Journal]
  74. S. Nandi, Parimal Pal Chaudhuri
    Reply to Comments on "Theory and Application of Cellular Automata in Cryptography". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:5, pp:639- [Journal]
  75. S. Nandi, B. K. Kar, Parimal Pal Chaudhuri
    Theory and Applications of Cellular Automata in Cryptography. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:12, pp:1346-1357 [Journal]
  76. Kolin Paul, Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri
    Theory of Extended Linear Machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:9, pp:1106-1110 [Journal]
  77. Koppolu Sasidhar, Santanu Chattopadhyay, Parimal Pal Chaudhuri
    CAA Decoder for Cellular Automata Based Byte Error Correcting Code. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:9, pp:1003-1016 [Journal]
  78. Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri
    KGPMIN: an efficient multilevel multioutput AND-OR-XOR minimizer. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:3, pp:257-265 [Journal]
  79. Baidya Nath Ray, Parimal Pal Chaudhuri, Prasanta Kumar Nandi
    Efficient synthesis of OTA network for linear analog functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:517-533 [Journal]
  80. Biplab K. Sikdar, Niloy Ganguly, Parimal Pal Chaudhuri
    Design of hierarchical cellular automata for on-chip test pattern generator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1530-1539 [Journal]
  81. Biplab K. Sikdar, Niloy Ganguly, Parimal Pal Chaudhuri
    Generation of test patterns without prohibited pattern set. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1650-1660 [Journal]
  82. Biplab K. Sikdar, Niloy Ganguly, Parimal Pal Chaudhuri
    Fault diagnosis of VLSI circuits with cellular automata based pattern classifier. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:1115-1131 [Journal]
  83. Pradipta Maji, Niloy Ganguly, Parimal Pal Chaudhuri
    Error correcting capability of cellular automata based associative memory. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Systems, Man, and Cybernetics, Part A, 2003, v:33, n:4, pp:466-480 [Journal]
  84. Pradipta Maji, Parimal Pal Chaudhuri
    RBFFCA: A Hybrid Pattern Classifier Using Radial Basis Function and Fuzzy Cellular Automata. [Citation Graph (0, 0)][DBLP]
    Fundam. Inform., 2007, v:78, n:3, pp:369-396 [Journal]
  85. Sukanta Das, Anirban Kundu, Biplab K. Sikdar, Parimal Pal Chaudhuri
    Design of Nonlinear CA Based TPG Without Prohibited Pattern Set In Linear Time. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:1, pp:95-107 [Journal]

  86. Theory and Application of Equal Length Cycle Cellular Automata (ELCCA) for Enzyme Classification. [Citation Graph (, )][DBLP]


  87. Programmable Cellular Automata (PCA) Based Advanced Encryption Standard (AES) Hardware Architecture. [Citation Graph (, )][DBLP]


  88. Probabilistic Cellular Automata Model for Identification of CpG island in DNA String. [Citation Graph (, )][DBLP]


  89. Design of Response-Pattern Classi er for Fault Diagnosis of Electronic Circuits. [Citation Graph (, )][DBLP]


  90. An Analytical Framework for Characterizing Restricted Two Dimensional Cellular Automata Evolution. [Citation Graph (, )][DBLP]


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